Computer Engineering Commons^™

The Thermal-Constrained Real-Time Systems Design On Multi-Core Platforms -- An Analytical Approach, Shi Sha

FIU Electronic Theses and Dissertations

Over the past decades, the shrinking transistor size enabled more transistors to be integrated into an IC chip, to achieve higher and higher computing performances. However, the semiconductor industry is now reaching a saturation point of Moore’s Law largely due to soaring power consumption and heat dissipation, among other factors. High chip temperature not only significantly increases packing/cooling cost, degrades system performance and reliability, but also increases the energy consumption and even damages the chip permanently. Although designing 2D and even 3D multi-core processors helps to lower the power/thermal barrier for single-core architectures by exploring the thread/process level parallelism, the …

Kicm: A Knowledge-Intensive Context Model, Fredrick Mtenzi, Denis Lupiana

Conference papers

A context model plays a significant role in developing context-aware architectures and consequently on realizing context-awareness, which is important in today's dynamic computing environments. These architectures monitor and analyse their environments to enable context-aware applications to effortlessly and appropriately respond to users' computing needs. These applications make the use of computing devices intuitive and less intrusive. A context model is an abstract and simplified representation of the real world, where the users and their computing devices interact. It is through a context model that knowledge about the real world can be represented in and reasoned by a context-aware architecture. This …

Stargrazer One: A New Architecture For Distributed Maximum Power Point Tracking Of Solar Photovoltaic Sources, Edgard Munoz-Coreas

Theses and Dissertations--Electrical and Computer Engineering

The yield from a solar photovoltaic (PV) source is dependent on factors such as light and temperature. A control system called a maximum power point tracker (MPPT) ensures that the yield from a solar PV source is maximized in spite of these factors. This thesis presents a novel implementation of a perturb and observe (PO) MPPT.

The implementation uses a switched capacitor step down converter and a custom digital circuit implementation of the PO algorithm. Working in tandem, the switched capacitor step down converter and the custom digital circuit implementation were able to successfully track the maximum power point of …

Fast Bitwise Pattern-Matching Algorithm For Dna Sequences On Modern Hardware, Giyasetti̇n Özcan, Osman Sabri̇ Ünsal

Turkish Journal of Electrical Engineering and Computer Sciences

We introduce a fast bitwise exact pattern-matching algorithm, which speeds up short-length pattern searches on large-sized DNA databases. Our contributions are two-fold. First, we introduce a novel exact matching algorithm designed specifically for modern processor architectures. Second, we conduct a detailed comparative performance analysis of bitwise exact matching algorithms by utilizing hardware counters. Our algorithmic technique is based on condensed bitwise operators and multifunction variables, which minimize register spills and instruction counts during searches. In addition, the technique aims to efficiently utilize CPU branch predictors and to ensure smooth instruction flow through the processor pipeline. Analyzing letter occurrence probability estimations …

On High-Performance Parallel Fixed-Point Decimal Multiplier Designs, Ming Zhu

UNLV Theses, Dissertations, Professional Papers, and Capstones

High-performance, area-efficient hardware implementation of decimal multiplication is preferred to slow software simulations in a number of key scientific and financial application areas, where errors caused by converting decimal numbers into their approximate binary representations are not acceptable.

Multi-digit parallel decimal multipliers involve two major stages: (i) the partial product generation (PPG) stage, where decimal partial products are determined by selecting the right versions of the pre-computed multiples of the multiplicand, followed by (ii) the partial product accumulation (PPA) stage, where all the partial products are shifted and then added together to obtain the final multiplication product. In this thesis, …

Modeling And Architectural Simulations Of The Statistical Static Timing Analysis Of The Variation Sources For Vlsi Circuits, Abu M. Baker

College of Engineering: Graduate Celebration Programs

As CMOS technology scales down, process variation introduces significant uncertainty in power and performance to VLSI circuits and significantly affects their reliability. Although Static-Timing Analysis (STA) remains an excellent tool, current trends in process scaling have imposed significant difficulties to STA. As one of the promising solutions, Statistical static timing analysis (SSTA) has become the frontier research topic in recent years in combating such variation effects. This poster will be focusing on two aspects of SSTA and its applications in VLSI designs: (1) Statistical timing modeling and analysis; and (2) Architectural implementations of the atomic operations (max and add) using …

Free Regions Of Sensor Nodes, Laxmi P. Gewali, Navin Rongatana, Henry Selvaraj, Jan B. Pedersen

Electrical & Computer Engineering Faculty Research

We introduce the notion of free region of a node in a sensor network. Intuitively, a free region of a node is the connected set of points R in its neighborhood such that the connectivity of the network remains the same when the node is moved to any point in R. We characterize several properties of free regions and develop an efficient algorithm for computing them. We capture free region in terms of related notions called in-free region and out-free region. We present an O(n2) algorithm for constructing the free region of a node, where n is the number of …

Dynamic Task Prediction For An Spmt Architecture Based On Control Independence, Komal Jothi

Dissertations and Theses

Exploiting better performance from computer programs translates to finding more instructions to execute in parallel. Since most general purpose programs are written in an imperatively sequential manner, closely lying instructions are always data dependent, making the designer look far ahead into the program for parallelism. This necessitates wider superscalar processors with larger instruction windows. But superscalars suffer from three key limitations, their inability to scale, sequential fetch bottleneck and high branch misprediction penalty. Recent studies indicate that current superscalars have reached the end of the road and designers will have to look for newer ideas to build computer processors.

Speculative …

Parallel Architectures For Solving Combinatorial Problems Of Logic Design, Phuong Minh Ho

Dissertations and Theses

This thesis presents a new, practical approach to solve various NP-hard combinatorial problems of logic synthesis, logic programming, graph theory and related areas. A problem to be solved is polynomially time reduced to one of several generic combinatorial problems which can be expressed in the form of the Generalized Propositional Formula (GPF) : a Boolean product of clauses, where each clause is a sum of products of negated or non-negated literals.