Computer Engineering Commons^™

Accelerating Machine Learning Inference For Satellite Component Feature Extraction Using Fpgas., Andrew Ekblad

Theses and Dissertations

Running computer vision algorithms requires complex devices with lots of computing power, these types of devices are not well suited for space deployment. The harsh radiation environment and limited power budgets have hindered the ability of running advanced computer vision algorithms in space. This problem makes running an on-orbit servicing detection algorithm very difficult. This work proposes using a low powered FPGA to accelerate the computer vision algorithms that enable satellite component feature extraction. This work uses AMD/Xilinx’s Zynq SoC and DPU IP to run model inference. Experiments in this work centered around improving model post processing by creating implementations …

Qasm-To-Hls: A Framework For Accelerating Quantum Circuit Emulation On High-Performance Reconfigurable Computers, Anshul Maurya

Theses and Dissertations

High-performance reconfigurable computers (HPRCs) make use of Field-Programmable Gate Arrays (FPGAs) for efficient emulation of quantum algorithms. Generally, algorithm-specific architectures are implemented on the FPGAs and there is very little flexibility. Moreover, mapping a quantum algorithm onto its equivalent FPGA emulation architecture is challenging. In this work, we present an automation framework for converting quantum circuits to their equivalent FPGA emulation architectures. The framework processes quantum circuits represented in Quantum Assembly Language (QASM) and derives high-level descriptions of the hardware emulation architectures for High-Level Synthesis (HLS) on HPRCs. The framework generates the code for a heterogeneous architecture consisting of a …

Design And Implementation Of A Low Cost And Portable Tactile Stimulator, Coşkun Kazma, Vecdi̇ Emre Levent, Merve Çardak, Ni̇zametti̇n Aydin

Turkish Journal of Electrical Engineering and Computer Sciences

When central nervous system has a problem, somatic area I and II respond to stimulation differently. Therefore, it is possible to identify some of the central nervous diseases when somatosensory on the fingertip is stimulated and responses are recorded and analyzed. We designed a system to stimulate the mechanoreceptors on fingertips. It is composed of a mechanical system for fingertip stimulation, an embedded controller, a control computer, and a software to control overall operation. During test, mechanoreceptors are stimulated according to the test protocols. Individuals' answers are recorded to be evaluated by the developed software. In this study, several design …

Evaluation Of Robust Deep Learning Pipelines Targeting Low Swap Edge Deployment, David Carter Cornett

Masters Theses

The deep learning technique of convolutional neural networks (CNNs) has greatly advanced the state-of-the-art for computer vision tasks such as image classification and object detection. These solutions rely on large systems leveraging wattage-hungry GPUs to provide the computational power to achieve such performance. However, the size, weight and power (SWaP) requirements of these conventional GPU-based deep learning systems are not suitable when a solution requires deployment to so called "Edge" environments such as autonomous vehicles, unmanned aerial vehicles (UAVs) and smart security cameras.

The objective of this work is to benchmark FPGA-based alternatives to conventional GPU systems that have the …

Domain Specific Computing In Tightly-Coupled Heterogeneous Systems, Anthony Michael Cabrera

McKelvey School of Engineering Theses & Dissertations

Over the past several decades, researchers and programmers across many disciplines have relied on Moores law and Dennard scaling for increases in compute capability in modern processors. However, recent data suggest that the number of transistors per square inch on integrated circuits is losing pace with Moores laws projection due to the breakdown of Dennard scaling at smaller semiconductor process nodes. This has signaled the beginning of a new “golden age in computer architecture” in which the paradigm will be shifted from improving traditional processor performance for general tasks to architecting hardware that executes a class of applications in a …

Compound Effects Of Clock And Voltage Based Power Side-Channel Countermeasures, Jacqueline Lagasse

Masters Theses

The power side-channel attack, which allows an attacker to derive secret information from power traces, continues to be a major vulnerability in many critical systems. Numerous countermeasures have been proposed since its discovery as a serious vulnerability, including both hardware and software implementations. Each countermeasure has its own drawback, with some of the highly effective countermeasures incurring large overhead in area and power. In addition, many countermeasures are quite invasive to the design process, requiring modification of the design and therefore additional validation and testing to ensure its accuracy. Less invasive countermeasures that do not require directly modifying the system …

Embedded Real Time Network Multimedia Data Transmission Method, Zaijian Wang, Ting Wan, Dandan Wu, Qingqing Xing

Journal of System Simulation

Abstract: To improve the speed of data acquisition and real-time video transmission, Filed Programmable Gate Array (FPGA) as the core processor, the Verilog HDL was used to describe the circuit function realization to realize the high-speed access of Synchronous Dynamic Random Access Memory (SDRAM) based on a typical network real-time transmission network multimedia service data. The new high-speed real-time transmission of video data took full advantage of the characteristics of FPGA parallel processing to improve video data acquisition and transmission rates. The experimental results demonstrate the effectiveness of the method.

An Fpga-Based Hardware Accelerator For The Digital Image Correlation Engine, Keaten Stokke

Graduate Theses and Dissertations

The work presented in this thesis was aimed at the development of a hardware accelerator for the Digital Image Correlation engine (DICe) and compare two methods of data access, USB and Ethernet. The original DICe software package was created by Sandia National Laboratories and is written in C++. The software runs on any typical workstation PC and performs image correlation on available frame data produced by a camera. When DICe is introduced to a high volume of frames, the correlation time is on the order of days. The time to process and analyze data with DICe becomes a concern when …

An Overlay Architecture For Pattern Matching, Rasha Elham Karakchi

Theses and Dissertations

Deterministic and Non-deterministic Finite Automata (DFA and NFA) comprise the fundamental unit of work for many emerging big data applications, motivating recent efforts to develop Domain-Specific Architectures (DSAs) to exploit fine-grain parallelism available in automata workloads.

This dissertation presents NAPOLY (Non-Deterministic Automata Processor Over- LaY), an overlay architecture and associated software that attempt to maximally exploit on-chip memory parallelism for NFA evaluation. In order to avoid an upper bound in NFA size that commonly affects prior efforts, NAPOLY is optimized for runtime reconfiguration, allowing for full reconfiguration in 10s of microseconds. NAPOLY is also parameterizable, allowing for offline generation of …

Simulation Of Electronic Transformer In Line With Ft3 Frame Format, Yu Fei, Hailong Zhang, Qingle Sun

Journal of System Simulation

Abstract: In the power system, electronic current transformer based on the Rogowski coil has been widely used in digital substation. Based on the analysis of its composition and structure, the electronic transformer is simulated by the Simulink module in Matlab. Rogowski coil is used to simulate the traditional transformer. Using Σ-Δ ADC converter and digital filter, analog signal from the high-pressure side is converted to digital output data, which is sent via fiber optic Ethernet to FPGA development board after FT3 format framing by Simulink. The data is then sent to the merged unit of transformer’s interface after Manchester encoding …

Accelerating Reverse Engineering Image Processing Using Fpga, Matthew Joshua Harris

Browse all Theses and Dissertations

In recent decades, field programmable gate arrays (FPGAs) have evolved beyond simple, expensive computational components with minimal computing power to complex, inexpensive computational engines. Today, FPGAs can perform algorithmically complex problems with improved performance compared to sequential CPUs by taking advantage of parallelization. This concept can be readily applied to the computationally dense field of image manipulation and analysis. Processed on a standard CPU, image manipulation suffers with large image sets processed by highly sequential algorithms, but by carefully adhering to data dependencies, parallelized FPGA functions or kernels offer the possibility of significant improvement through threaded CPU functions. This thesis …

Leveraging Blockchain To Mitigate The Risk Of Counterfeit Microelectronics In Its Supply Chain, Aman Ali Pogaku

Browse all Theses and Dissertations

System on Chip (SoC) is the backbone component of the electronics industry nowadays. ASIC and FPGA-based SoCs are the two most popular methods of manufacturing SoCs. However, both ASIC and FPGA industries are plagued with risks of counterfeits due to the limitations in Security, Accountability, Complexity, and Governance of their supply chain management. As a result, the current practices of these microelectronics supply chain suffer from performance and efficiency bottlenecks. In this research, we are incorporating blockchain technology into the FPGA and ASIC microelectronic supply chain to help mitigate the risk of counterfeit microelectronics through a secure and decentralized solution …

Compact Hardware Implementation Of A Sha-3 Core For Wireless Body Sensor Networks, Yi Yang, Debiao He, Neeraj Kumar, Sherali Zeadally

Information Science Faculty Publications

One of the most important Internet of Things applications is the wireless body sensor network (WBSN), which can provide universal health care, disease prevention, and control. Due to large deployments of small scale smart sensors in WBSNs, security, and privacy guarantees (e.g., security and safety-critical data, sensitive private information) are becoming a challenging issue because these sensor nodes communicate using an open channel, i.e., Internet. We implement data integrity (to resist against malicious tampering) using the secure hash algorithm 3 (SHA-3) when smart sensors in WBSNs communicate with each other using the Internet. Due to the limited resources (i.e., storage, …

Progressive Network Deployment, Performance, And Control With Software-Defined Networking, Daniel J. Casey

Theses and Dissertations

The inflexible nature of traditional computer networks has led to tightly-integrated systems that are inherently difficult to manage and secure. New designs move low-level network control into software creating software-defined networks (SDN). Augmenting an existing network with these enhancements can be expensive and complex. This research investigates solutions to these problems. It is hypothesized that an add-on device, or "shim" could be used to make a traditional switch behave as an OpenFlow SDN switch while maintaining reasonable performance. A design prototype is found to cause approximately 1.5% reduction in throughput for one ow and less than double increase in latency, …

Highly Accurate And Sensitive Short Read Aligner, Mehmet Yağmur Gök, Sezer Gören Uğurdağ, Cem Ünsalan, Mahmut Şami̇l Sağiroğlu

Turkish Journal of Electrical Engineering and Computer Sciences

Next-generation sequencing generates large numbers of short reads from DNA. This makes it difficult to process and store. Therefore, efficient sequence alignment and mapping techniques are needed in bioinformatics. Alignment and mapping are the basic steps involved in genetic data analysis. The Smith-Waterman (SW) algorithm, a well-known dynamic programming algorithm, is often used for this purpose. In this work, we propose to utilize Phred quality scores in Gotoh's affine gap model to increase the accuracy and sensitivity of the SW algorithm. Hardware platforms such as FPGAs and GPUs are commonly used to solve computationally expensive problems. In this work, a …

A Proposed Approach To Hybrid Software-Hardware Application Design For Enhanced Application Performance, Alex Shipman

Graduate Theses and Dissertations

One important aspect of many commercial computer systems is their performance; therefore, system designers seek to improve the performance next-generation systems with respect to previous generations. This could mean improved computational performance, reduced power consumption leading to better battery life in mobile devices, smaller form factors, or improvements in many areas. In terms of increased system speed and computation performance, processor manufacturers have been able to increase the clock frequency of processors up to a point, but now it is more common to seek performance gains through increased parallelism (such as a processor having more processor cores on a single …

A Hybrid Partially Reconfigurable Overlay Supporting Just-In-Time Assembly Of Custom Accelerators On Fpgas, Zeyad Tariq Aklah

Graduate Theses and Dissertations

The state of the art in design and development flows for FPGAs are not sufficiently mature to allow programmers to implement their applications through traditional software development flows. The stipulation of synthesis as well as the requirement of background knowledge on the FPGAs' low-level physical hardware structure are major challenges that prevent programmers from using FPGAs. The reconfigurable computing community is seeking solutions to raise the level of design abstraction at which programmers must operate, and move the synthesis process out of the programmers' path through the use of overlays. A recent approach, Just-In-Time Assembly (JITA), was proposed that enables …

Network-On-Chip Based H.264 Video Decoder On A Field Programmable Gate Array, Ian Barge

Master's Theses (2009 -)

This thesis develops the first fully network-on-chip (NoC) based h.264 video decoder implemented in real hardware on a field programmable gate array (FPGA). This thesis starts with an overview of the h.264 video coding standard and an introduction to the NoC communication paradigm. Following this, a series of processing elements (PEs) are developed which implement the component algorithms making up the h.264 video decoder. These PEs, described primarily in VHDL with some Verilog and C, are then mapped to an NoC which is generated using the CONNECT NoC generation tool. To demonstrate the scalability of the proposed NoC based design, …

Modeling And Control Of A Permanent-Magnet Brushless Dc Motor Drive Using A Fractional Order Proportional-Integral-Derivative Controller, Swapnil Khubalkar, Anjali Junghare, Mohan Aware, Shantanu Das

Turkish Journal of Electrical Engineering and Computer Sciences

This paper deals with the speed control of a permanent-magnet brushless direct current (PMBLDC) motor. A fractional order PID (FOPID) controller is used in place of the conventional PID controller. The FOPID controller is a generalized form of the PID controller in which the order of integration and differentiation is any real number. It is shown that the proposed controller provides a powerful framework to control the PMBLDC motor. Parameters of the controller are found by using a novel dynamic particle swarm optimization (dPSO) method. The frequency domain pole-zero (p-z) interlacing method is used to approximate the fractional order operator. …

Analysis Of 3d Cone-Beam Ct Image Reconstruction Performance On A Fpga, Devin Held

Electronic Thesis and Dissertation Repository

Efficient and accurate tomographic image reconstruction has been an intensive topic of research due to the increasing everyday usage in areas such as radiology, biology, and materials science. Computed tomography (CT) scans are used to analyze internal structures through capture of x-ray images. Cone-beam CT scans project a cone-shaped x-ray to capture 2D image data from a single focal point, rotating around the object. CT scans are prone to multiple artifacts, including motion blur, streaks, and pixel irregularities, therefore must be run through image reconstruction software to reduce visual artifacts. The most common algorithm used is the Feldkamp, Davis, and …

High Dynamic Performance Of A Bldc Motor With A Front End Converter Using An Fpga Based Controller For Electric Vehicle Application, Praveen Yadav, Rajesh Poola, Khaja Najumudeen

Turkish Journal of Electrical Engineering and Computer Sciences

This paper focus on a novel operation of a brushless dc (BLDC) motor fed by a proportional integral (PI) controlled buck--boost converter supplemented with a battery to provide the required power to drive the BLDC motor. The operational characteristics of the proposed BLDC motor drive system for constant as well as step changes in dc link voltage of a front end converter controlled by a Xilinx System Generator (XSG) based PI controller for two quadrant operations are derived. Thus a field programmable gate array (FPGA) based PI controller manages the energy flow through the battery and the front end converter. …

Fpga Implementation Of A Hevc Deblocking Filter For Fast Processing Of Super High Resolution Applications, Awais Khan, Gulistan Raja

Turkish Journal of Electrical Engineering and Computer Sciences

This paper proposes the architecture of a deblocking filter (DBF) that removes blocking artifacts in new emerging High Efficiency Video Coding (HEVC). A parallel architecture for both normal and strong filtering modes of HEVC is proposed. Distributed memories and two data paths increase the parallelism and make the architecture more efficient. The proposed architecture is described by Verilog and implemented on FPGA. The architecture can realize real time to compute 4K UHD video at 30 fps by using 46.65 million clocks with total equivalent gate count of 46K. The maximum delay time for output to come after taking input for …

Implementation Of A Modified Svpwm-Based Three-Phase Inverter With Reduced Switches Using A Single Dc Source For A Grid-Connected Pv System, Venkatesan Mani, Rajeswari Ramachandran, Deverajan Nanjundappan

Turkish Journal of Electrical Engineering and Computer Sciences

No abstract provided.

An Alternative Carry-Save Arithmetic For New Generation Field Programmable Gate Arrays, Uğur Çi̇ni̇, Mustafa Aktan, Avni̇ Morgül

Turkish Journal of Electrical Engineering and Computer Sciences

In this work, a double carry-save addition operation is proposed, which is efficiently synthesized for 6-input LUT-based field programmable gate arrays (FPGAs). The proposed arithmetic operation is based on redundant number representation and provides carry propagation-free addition. Using the proposed arithmetic operation, a compact and fast multiply and accumulate unit is designed. To our knowledge, the proposed design provides the fastest multiply-add operation for 6-input LUT-based FPGA systems. A finite impulse response filter implementation is given to show the performance of the proposed structure. The proposed implementation provides a dramatic performance increase, which is at least 2 times faster than …

Towards Real-Time, On-Board, Hardware-Supported Sensor And Software Health Management For Unmanned Aerial Systems, Johann M. Schumann, Kristin Y. Rozier, Thomas Reinbacher, Ole J. Mengshoel, Timmy Mbaya, Corey Ippolito

Ole J Mengshoel

Designing And Implementing A Reliable Thermal Monitoring System Based On The 1-Wire Protocol On Fpga For A Leo Satellite, Reza Omidi Gosheblagh, Karim Mohammadi

Turkish Journal of Electrical Engineering and Computer Sciences

Thermal control and monitoring is one of the most important factors in the design of satellite systems. An appropriate thermal design should make sure that the satellite's sensitive components remain in their nominated range, even under the vacuum condition of outer space. To achieve this purpose, a reliable and stable monitoring system is required. This paper proposes a monitoring system based on the 1-wire protocol, which provides the reliability requirements in the sensor networking and bus controller sections. In the networking section, we outline some practical topologies and discuss on their complexity and reliability. Despite the fact that the point-to-point …

Reconfigurable Technologies For Next Generation Internet And Cluster Computing, Deepak C. Unnikrishnan

Open Access Dissertations

Modern web applications are marked by distinct networking and computing characteristics. As applications evolve, they continue to operate over a large monolithic framework of networking and computing equipment built from general-purpose microprocessors and Application Specific Integrated Circuits (ASICs) that offers few architectural choices. This dissertation presents techniques to diversify the next-generation Internet infrastructure by integrating Field-programmable Gate Arrays (FPGAs), a class of reconfigurable integrated circuits, with general-purpose microprocessor-based techniques. Specifically, our solutions are demonstrated in the context of two applications - network virtualization and distributed cluster computing.

Network virtualization enables the physical network infrastructure to be shared among several …

System Designs To Perform Bioinformatics Sequence Alignment, Çağlar Yilmaz, Mustafa Gök

Turkish Journal of Electrical Engineering and Computer Sciences

The emerging field of bioinformatics uses computing as a tool to understand biology. Biological data of organisms (nucleotide and amino acid sequences) are stored in databases that contain billions of records. In order to process the vast amount of data in a reasonable time, high-performance analysis systems are developed. The main operation shared by the analysis tools is the search for matching patterns between sequences of data (sequence alignment). In this paper, we present 2 systems that can perform pairwise and multiple sequence alignment operations. Through the optimized design methods, proposed systems achieve up to 3.6 times more performance compared …

Hardware-Software Co-Design, Acceleration And Prototyping Of Control Algorithms On Reconfigurable Platforms, Desta Kumsa Edosa

UNLV Theses, Dissertations, Professional Papers, and Capstones

Differential equations play a significant role in many disciplines of science and engineering. Solving and implementing Ordinary Differential Equations (ODEs) and partial Differential Equations (PDEs) effectively are very essential as most complex dynamic systems are modeled based on these equations. High Performance Computing (HPC) methodologies are required to compute and implement complex and data intensive applications modeled by differential equations at higher speed. There are, however, some challenges and limitations in implementing dynamic system, modeled by non-linear ordinary differential equations, on digital hardware. Modeling an integrator involves data approximation which results in accuracy error if data values are not considered …

Low-Cost Stereo Vision On An Fpga, Chris A. Murphy, Daniel Lindquist, Ann Marie Rynning, Thomas Cecil, Sarah Leavitt, Mark L. Chang

Mark L. Chang

We present a low-cost stereo vision implementation suitable for use in autonomous vehicle applications and designed with agricultural applications in mind. This implementation utilizes the Census transform algorithm to calculate depth maps from a stereo pair of automotive-grade CMOS cameras. The final prototype utilizes commodity hardware, including a Xilinx Spartan-3 FPGA, to process 320times240 pixel images at greater than 150 frames per second and deliver them via a USB 2.0 interface.