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Articles 31 - 60 of 683
Full-Text Articles in Computer Engineering
Migrating To Ipv6 - The Role Of Basic Coordination, Mehdi Nikkhah, Roch Guerin
Migrating To Ipv6 - The Role Of Basic Coordination, Mehdi Nikkhah, Roch Guerin
All Computer Science and Engineering Research
The need for a larger Internet address space was acknowledged early on, and a solution (IPv6) standardized years ago. Its adoption has, however, been anything but easy and still faces significant challenges. The situation begs the questions of "why has it been so difficult?" and "what could have been (or still be) done to facilitate this migration?" There has been significant recent interest in those questions, and the paper builds on a line of work based on technology adoption models to explore them. The results confirm the impact of several known factors, but also provide new insight. In particular, they …
Capacity Augmentation Bound Of Federated Scheduling For Parallel Dag Tasks, Jing Li, Abusayeed Saifullah, Kunal Agrawal, Christopher Gill
Capacity Augmentation Bound Of Federated Scheduling For Parallel Dag Tasks, Jing Li, Abusayeed Saifullah, Kunal Agrawal, Christopher Gill
All Computer Science and Engineering Research
We present a novel federated scheduling approach for parallel real-time tasks under a general directed acyclic graph (DAG) model. We provide a capacity augmentation bound of 2 for hard real-time scheduling; here we use the worst-case execution time and critical-path length of tasks to determine schedulability. This is the best known capacity augmentation bound for parallel tasks. By constructing example task sets, we further show that the lower bound on capacity augmentation of federated scheduling is also 2 for any m > 2. Hence, the gap is closed and bound 2 is a strict bound for federated scheduling. The federated scheduling …
Federated Scheduling For Stochastic Parallel Real-Time Tasks, Jing Li, Kunal Agrawal, Christopher Gill, Chenyang Lu
Federated Scheduling For Stochastic Parallel Real-Time Tasks, Jing Li, Kunal Agrawal, Christopher Gill, Chenyang Lu
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Federated scheduling is a strategy to schedule parallel real-time tasks: It allocates a dedicated cluster of cores to high-utilization task (utilization >1); It uses a multiprocessor scheduling algorithm to schedule and execute all low-utilization tasks sequentially, on a shared cluster of the remaining cores. Prior work has shown that federated scheduling has the best known capacity augmentation bound of 2 for parallel tasks with implicit deadlines. In this paper, we explore the soft real-time performance of federated scheduling and address the average-case workloads instead of the worst-case values. In particular, we consider stochastic tasks -- tasks for which execution time …
Rt-Openstack: A Real-Time Cloud Management System, Sisu Xi, Chong Li, Chenyang Lu, Christopher D. Gill, Meng Xu, Linh T.X. Phan, Insup Lee, Oleg Sokolsky
Rt-Openstack: A Real-Time Cloud Management System, Sisu Xi, Chong Li, Chenyang Lu, Christopher D. Gill, Meng Xu, Linh T.X. Phan, Insup Lee, Oleg Sokolsky
All Computer Science and Engineering Research
Clouds have become appealing platforms for running not only general-purpose applications but also real-time applications. However, current clouds cannot provide real-time performance for virtual machines (VM) for two reasons: (1) the lack of a real-time virtual machine monitor (VMM) scheduler on a single host, and (2) the lack of a real-time aware VM placement scheme by the cloud manager. While real-time VM schedulers do exist, prior solutions employ either heuristics-based approaches that cannot always achieve predictable latency or apply real-time scheduling theory that may result in low CPU utilization. We observe the demand and advantage for co-hosting real-time (RT) VMs …
Cloudpowercap: Integrating Power Budget And Resource Management Across A Virtualized Server Cluster, Yong Fu, Anne Holler, Chenyang Lu
Cloudpowercap: Integrating Power Budget And Resource Management Across A Virtualized Server Cluster, Yong Fu, Anne Holler, Chenyang Lu
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In many datacenters, server racks are highly underutilized. Rack slots are left empty to keep the sum of the server nameplate maximum power below the power provisioned to the rack. And the servers that are placed in the rack cannot make full use of available rack power. The root cause of this rack underutilization is that the server nameplate power is often much higher than can be reached in practice. To address rack underutilization, server vendors are shipping support for per-host power caps, which provide a server-enforced limit on the amount of power that the server can draw. Using this …
Performance Modeling Of Virtualized Custom Logic Computations, Michael J. Hall, Roger D. Chamberlain
Performance Modeling Of Virtualized Custom Logic Computations, Michael J. Hall, Roger D. Chamberlain
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Virtualization of custom logic computations (i.e., by sharing a fixed function across distinct data streams) provides a means of reusing hardware resources, particularly when resources are limited. This is common practice in traditional processors where more than one user can share processor resources. In this paper, we virtualize a custom logic block using C-slow techniques to support fine-grain context-switching. We then develop and present an analytic model for several performance measures (throughput, latency, input queue occupancy) for both fine-grained and coarse-grained context switching (to a secondary memory). Next, we calibrate the analytic performance model with empirical measurements. We then validate …
Inferring Memory Map Instructions, Paul T. Scheid, Ari J. Spilo, Ron K. Cytron
Inferring Memory Map Instructions, Paul T. Scheid, Ari J. Spilo, Ron K. Cytron
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We describe the problem of inferring a set of memory map instructions from a reference trace, with the goal of minimizing the number of such instructions as well as the number of unreferenced but mapped storage locations. We prove the related decision problem NP-complete. We then present and compare the results of two heuristic approaches on some actual traces.
Streaming Computations With Precise Control, Peng Li, Kunal Agrawal, Jeremy Buhler, Roger Chamberlain
Streaming Computations With Precise Control, Peng Li, Kunal Agrawal, Jeremy Buhler, Roger Chamberlain
All Computer Science and Engineering Research
No abstract provided.
Adding Data Parallelism To Streaming Pipelines For Throughput Optimization, Peng Li, Kunal Agrawal, Jeremy Buhler, Roger D. Chamberlain
Adding Data Parallelism To Streaming Pipelines For Throughput Optimization, Peng Li, Kunal Agrawal, Jeremy Buhler, Roger D. Chamberlain
All Computer Science and Engineering Research
The streaming model is a popular model for writing high-throughput parallel applications. A streaming application is represented by a graph of computation stages that communicate with each other via FIFO channels. In this report, we consider the problem of mapping streaming pipelines — streaming applications where the graph is a linear chain — in order to maximize throughput. In a parallel setting, subsets of stages, called components can be mapped onto different computing resources. The through-put of an application is determined by the throughput of the slowest component. Therefore, if some stage is much slower than others, then it may …
Automated Color Calibration Of Display Devices, Andrew Shulman
Automated Color Calibration Of Display Devices, Andrew Shulman
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If you compare two identical images on two different monitors, they will likely appear different. Every display device is supposed to adhere to a particular set of standards regulating the color and intensity of the image it outputs. However, in practice, very few do. Color calibration is the practice of modifying the signal path such that the colors produced more closely match reference standards. This is essential for graphics professionals who are mastering original content. They must ensure that the source material appears correct when viewed on a reference monitor. When viewed on a consumer panel, however, some error will …
Ewa Model With Recency Effect And Limited Memory, Hang Xie
Ewa Model With Recency Effect And Limited Memory, Hang Xie
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Game theory is an important field in economics; it studies how people make decisions amid conflict and cooperation. Various experiments have been carried to study the way people play those games, and economists study those data for various purposes. There has been a rise of need for using artificial agents to simulate the game, since we could save the cost of hiring human subjects for the experiments, and we could gain more control over the experiment settings.
Efficient Parallel Real-Time Upsampling Of Ultrasound Vectors, William D. Richard Ph.D.
Efficient Parallel Real-Time Upsampling Of Ultrasound Vectors, William D. Richard Ph.D.
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Upsampling is required prior to the summation step in most receive digital beamforming implementations to produce an accurate summed RF line or vector. This is true in both annular and linear array systems where receive echos are digitized first and then time delayed in the digital domain to achieve proper signal alignment. The efficient, parallel, real-time upsampling circuit presented here produces M upsampled values per ADC clock, where M is the desired upsampling factor. A circuit implementation that upsamples by a factor of M=4 is presented as an example of the more general technique.
Kernel Density Metric Learning, Yujie He, Wenlin Chen, Yixin Chen
Kernel Density Metric Learning, Yujie He, Wenlin Chen, Yixin Chen
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This paper introduces a supervised metric learning algorithm, called kernel density metric learning (KDML), which is easy to use and provides nonlinear, probability-based distance measures. KDML constructs a direct nonlinear mapping from the original input space into a feature space based on kernel density estimation. The nonlinear mapping in KDML embodies established distance measures between probability density functions, and leads to correct classification on datasets for which linear metric learning methods would fail. Existing metric learning algorithms, such as large margin nearest neighbors (LMNN), can then be applied to the KDML features to learn a Mahalanobis distance. We also propose …
Parallel Real-Time Scheduling Of Dags, Abusayeed Saifullah, David Ferry, Jing Li, Kunal Agrawal, Chenyang Lu, Christopher Gill
Parallel Real-Time Scheduling Of Dags, Abusayeed Saifullah, David Ferry, Jing Li, Kunal Agrawal, Chenyang Lu, Christopher Gill
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Recently, multi-core processors have become mainstream in processor design. To take full advantage of multi-core processing, computation-intensive real-time systems must exploit intra-task parallelism. In this paper, we address the open problem of real-time scheduling for a general model of deterministic parallel tasks, where each task is represented as a directed acyclic graph (DAG) with nodes having arbitrary execution requirements. We prove processor-speed augmentation bounds for both preemptive and non-preemptive real-time scheduling for general DAG tasks on multi-core processors. We first decompose each DAG into sequential tasks with their own release times and deadlines. Then we prove that these decomposed tasks …
Simple Analytic Performance Models For Streaming Data Applications Deployed On Diverse Architectures, Jonathan C. Beard, Roger D. Chamberlain, Mark A. Franklin
Simple Analytic Performance Models For Streaming Data Applications Deployed On Diverse Architectures, Jonathan C. Beard, Roger D. Chamberlain, Mark A. Franklin
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Modern hardware is inherently heterogeneous. With heterogeneity comes multiple abstraction layers that hide underlying complex systems. While hidden, this complexity makes quantitative performance modeling a difficult task. Designers of high-performance streaming applications for heterogeneous systems must contend with unpredictable and often non-generalizable models to predict performance of a particular application and hardware mapping. This paper outlines a computationally simple approach that can be used to model the overall throughput and buffering needs of a streaming application on heterogeneous hardware. The model presented is based upon a hybrid maximum flow and decomposed discrete queueing model. The utility of the model is …
Real-Time Multi-Core Virtual Machine Scheduling In Xen, Sisu Xi, Meng Xu, Chenyang Lu, Linh T.X. Phan, Christopher Gill, Olga Sokolsky, Insup Lee
Real-Time Multi-Core Virtual Machine Scheduling In Xen, Sisu Xi, Meng Xu, Chenyang Lu, Linh T.X. Phan, Christopher Gill, Olga Sokolsky, Insup Lee
All Computer Science and Engineering Research
Recent years have witnessed two major trends in the development of complex real-time systems. First, to reduce cost and enhance flexibility, multiple systems are sharing common computing platforms via virtualization technology, instead of being deployed separately on physically isolated hosts. Second, multicore processors are increasingly being used in real-time systems. The integration of real-time systems as virtual machines (VMs) atop common multicore platforms raises significant new research challenges in meeting the real-time performance requirements of multiple systems.
Scanner: An Efficient And Accurate Trimming Tool For Illumina Next Generation Sequencing Reads, Xiang Zhou
Scanner: An Efficient And Accurate Trimming Tool For Illumina Next Generation Sequencing Reads, Xiang Zhou
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Recent advances in High-Throughput Sequencing (HTS) technology have greatly facilitated the researches in bioinformatics field. With the ultra-high sequencing speed and improved base-calling accuracy, Illumina Genome Analyzer is currently the most widely used platform in the field. To use the raw reads generated from the sequencing machine, the 3’ adapter sequence attached to the real read in the process of ligation needs to be correctly trimmed. This is often done by some inhouse scripts or different packages with various parameters. They either use the Smith-Waterman algorithm or search for an exact match of the 3’ adapter sequence. In this report, …
Self-Adapting Mac Layer For Wireless Sensor Networks, Mo Sha, Meng Xu, Chenyang Lu, Linh T.X. Phan, Tae-Suk Kim, Taerim Park
Self-Adapting Mac Layer For Wireless Sensor Networks, Mo Sha, Meng Xu, Chenyang Lu, Linh T.X. Phan, Tae-Suk Kim, Taerim Park
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The integration of wireless sensors with mobile phones is gaining momentum as an enabling platform for numerous emerging applications. These mobile systems face dynamic environments where both application requirements and ambient wireless conditions change frequently. Despite the existence of many MAC protocols however, none can provide optimal performance along multiple dimensions, in particular when the conditions are frequently changing. Instead of pursuing a one-MAC-fit all approach we present a Self-Adapting MAC Layer (SAML) comprising (1) a Reconfigurable MAC Architecture (RMA) that can switch to different MAC protocols at run time and (2) a learning-based MAC Selection Engine that selects the …
Accounting For Failures In Delay Analysis For Wirelesshart Networks , Abusayeed Saifullah, Paras Babu Tiwari, Bo Li, Chenyang Lu Lu@Wustl.Edu
Accounting For Failures In Delay Analysis For Wirelesshart Networks , Abusayeed Saifullah, Paras Babu Tiwari, Bo Li, Chenyang Lu Lu@Wustl.Edu
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WirelessHART networks are gaining ground as a real-time communication infrastructure in industrial wireless control systems. Because wireless communication is often susceptible to transmission failures in industrial environments, it is essential to account for failures in the delay analysis for realtime flows between sensors and actuators in process control. WirelessHART networks handle transmission failures through retransmissions using dedicated and shared time slots through different paths in the routing graphs. While these mechanisms for handling transmission failures are critical for process control requiring reliable communication, they introduce substantial challenges to worst-case end-to-end delay analysis for real-time flows. This paper presents the first …
Correction Of An Augmentation Bound Analysis For Parallel Real-Time Tasks, Abusayeed Saifullah, Kunal Agrawal, Chenyang Lu, Christopher Gill
Correction Of An Augmentation Bound Analysis For Parallel Real-Time Tasks, Abusayeed Saifullah, Kunal Agrawal, Chenyang Lu, Christopher Gill
All Computer Science and Engineering Research
This paper proposes some significant corrections in a recent work of Lakshmanan et al on parallel task scheduling. Lakshmanan et al have proposed a transformation of parallel tasks into sequential tasks, and have claimed a resource augmentation bound of 3:42 for partitioned deadline monotonic (DM) scheduling of the transformed tasks. We demonstrate that their analysis for resource augmentation bound is incorrect. We propose a different technique for task transformation that requires a resource augmentation bound of 5 for partitioned DM scheduling.
Early Warning System: Relay Sensor Deployment & Network Reliability Analysis, Zhicheng Yang
Early Warning System: Relay Sensor Deployment & Network Reliability Analysis, Zhicheng Yang
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In this project, we continued Dr. Chipara's study, which developed an early warning system (EWS) to detect the vital signs of patients in order to help doctors to intervene in time [1]. Since the number of wards increased, the environment our system faced with became more complicated and our network became more sensitive. This project focused on finding reasons on the relays that didn't work and doing a reliability analysis on the network in one ward our study covered.
Ride: A Mixed-Mode Control Interface For Mobile Robot Teams, Erik Karulf, Marshall Strother, Parker Dunton, William D. Smart
Ride: A Mixed-Mode Control Interface For Mobile Robot Teams, Erik Karulf, Marshall Strother, Parker Dunton, William D. Smart
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There is a growing need for robot control interfaces that allow a single user to effectively control a large number of mostly-autonomous robots. The challenges in controlling such a collection of robots are very similar to the challenges of controlling characters in some genres of video games. In this paper, we argue that interfaces based on elements from computer video games are effective tools for the control of large robot teams. We present RIDE, the Robot Interactive Display Environment, an example of such an interface, and give the results of initial user studies with the interface, which lend support to …
Kinect Hand Recognition And Tracking, Alex Drake
Kinect Hand Recognition And Tracking, Alex Drake
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he goal of this research project was to be able to identify and track a hand using the depth image from a Microsoft Kinect. The ability to do this would have uses in sign language recognition, rehabilitation, and gesture recognition amongst others. The Microsoft Kinect is currently capable of identifying and tracking whole bodies. Our approach was to follow the method that Microsoft used but apply it to detailed hand recognition instead of the body. The basic strategy they used was to take a large amount of labeled depth data and build a decision tree to identify which part of …
Specializing Interfaces For Citizen Science Segmentation Of Volumetric Data, Michelle Vaughan, Cindy Grimm, Ruth Sowell, Robert Pless, Stephen Kobourov
Specializing Interfaces For Citizen Science Segmentation Of Volumetric Data, Michelle Vaughan, Cindy Grimm, Ruth Sowell, Robert Pless, Stephen Kobourov
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Segmentation of 3D and time-varying volumetric (4D) image data is considered a time and resource intensive bottleneck in scientific endeavors. Automatic methods are becoming more reliable, but many data sets still require manual intervention. This can mainly be attributed to the characteristics of the image data not being amenable to automated methods, the existence of variations in or poor image quality, or the need for an expert to review and edit results from an automatic technique. Manually segmenting volumetric data is a challenge even for those more experienced. Understanding the 3D nature of the data and navigating through the 3D …
Just Draw It! A 3d Sketching System, Cindy Grimm, Pushkar Joshi
Just Draw It! A 3d Sketching System, Cindy Grimm, Pushkar Joshi
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We present a system for sketching in 2D to create 3D curves. The interface is light-weight, pen-based, and based on observations of how artists sketch on paper.
Data Collection And Performance Monitoring Of Real-Time Parallel Systems , Mahesh Mahadevan
Data Collection And Performance Monitoring Of Real-Time Parallel Systems , Mahesh Mahadevan
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Instrumentation and log data monitoring are important features present in many different applications today that are used in analysis of a system behaviour. They are largely used in collection of key information from the system which might allow us to describe or establish certain facts about the behavior of the system. Instrumentation in any application usually comes along with its overheads. In some cases , code for instrumentation might become more expensive on the underlying resources than the application itself. For many applications, especially real-time applications , this overhead can cause serious and often catastrophic system failures. Collecting useful information …
A 3d Selection & Query Tool For The Geneatlas Project, Donald Mccurdy
A 3d Selection & Query Tool For The Geneatlas Project, Donald Mccurdy
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In this project, I present an application to view, interact with, and search 3D medical volumes as part of the GeneAtlas project.
Common Dma Engine Interface, Roger Alessi
Common Dma Engine Interface, Roger Alessi
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Circuit boards with Field Programmable Gate Arrays (FPGAs) have a historically diverse set of standards for communicating with other devices. This provides a challenge for developers creating FPGA applications and makes migration of applications from one board or FPGA to another difficult. Many board manufacturers, including Xilinx and GiDEL, create boards with Peripheral Component Interconnect Express (PCIe) buses. PCIe provides a low-level standard for transferring data between a Central Processing Unit (CPU) and an FPGA, and these manufacturers have designed Direct Memory Access (DMA) engines to implement the standard. However, each manufacturer’s DMA engines do not share a standard interface, …
A Memory Access Model For Highly-Threaded Many-Core Architectures, Lin Ma, Kunal Agrawal, Roger D. Chamberlain
A Memory Access Model For Highly-Threaded Many-Core Architectures, Lin Ma, Kunal Agrawal, Roger D. Chamberlain
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Many-core architectures are excellent in hiding memory-access latency by low-overhead context switching among a large number of threads. The speedup of algorithms carried out on these machines depends on how well the latency is hidden. If the number of threads were infinite, then theoretically these machines should provide the performance predicted by the PRAM analysis of the programs. However, the number of allowable threads per processor is not infinite. In this paper, we introduce the Threaded Many-core Memory (TMM) model which is meant to capture the important characteristics of these highly-threaded, many-core machines. Since we model some important machine parameters …
Building A Skeleton Of A Human Hand Using Microsoft Kinect, Jed Jackoway
Building A Skeleton Of A Human Hand Using Microsoft Kinect, Jed Jackoway
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The goal of the project was to reconstruct the skeleton of a Microsoft Kinect user’s hand. Out of the box, Kinect reconstruct the skeleton of users’ bodies, but it only does large joints, such that the hand is given a location on the general skeleton, but the specifics of the fingers and fist are not actually calculated.