Engineering Commons^™

Propositions For A Resilient, Post-Covid-19 Future For The Aec Industry, Hala Nassereddine, Kyung Wook Seo, Zofia K. Rybkowski, Christian Schranz, Harald Urban

Civil Engineering Faculty Publications

The coronavirus outbreak has challenged and continues to challenge every aspect of the supply chain within the AEC industry, forcing stakeholders to cope with increasing uncertainties and continuous change. The notion of resilience is especially salient now. While the need for the AEC industry to focus on resilience has been highlighted in recent articles, there is a need for a comprehensive discussion on what resilience means for the AEC industry and how companies can create built-in resilience. This paper takes the form of a high-level overview of where the industry is headed and aims to establish eleven propositions for a …

Adiabatic Logic-In-Memory Architecture, Himanshu Thapliyal, S. Dinesh Kumar

Electrical and Computer Engineering Faculty Patents

An adiabatic logic-in-memory based complementary metal- oxide-semiconductor/magnetic-tunnel-junction (ALiM CMOS/MTJ) circuit utilizes an adiabatic logic based pre- charged sense amplifier (PCSA) to recover energy from its output load capacitors. The ALiM CMOS/MTJ includes a non-volatile magnetic-tunnel-junction (MTJ) based memory. The ALiM CMOS/MTJ also includes a dual rail complementary metal-oxide-semiconductor (CMOS) logic that performs logic operations in association with the MTJ, and thereby generates logic outputs based on logic inputs. The ALiM CMOS/MTJ also includes the adiabatic PCSA, which is operatively coupled to the dual rail CMOS logic. The adiabatic logic based PCSA includes PCSA circuitry for which an input is a …

A Compiler Target Model For Line Associative Registers, Paul S. Eberhart

Theses and Dissertations--Electrical and Computer Engineering

LARs (Line Associative Registers) are very wide tagged registers, used for both register-wide SWAR (SIMD Within a Register )operations and scalar operations on arbitrary fields. LARs include a large data field, type tags, source addresses, and a dirty bit, which allow them to not only replace both caches and registers in the conventional memory hierarchy, but improve on both their functions. This thesis details a LAR-based architecture, and describes the design of a compiler which can generate code for a LAR-based design. In particular, type conversion, alignment, and register allocation are discussed in detail.

What You Don’T See, Brent Sturlaugson

Architecture Faculty Publications

Follow the supply chains of architecture and you’ll find not just product manufacturers but also environmental polluters and elusive networks of financial power and political influence.

Intelligent Transportation Systems Statewide Architecture, Joseph D. Crabtree, Jennifer R. Walton

Kentucky Transportation Center Research Report

This report describes the development of Kentucky’s Statewide Intelligent Transportation Systems (ITS) Architecture. The process began with the development of an ITS Strategic Plan in 1997-2000. A Business Plan, developed in 2000-2001, translated the goals of the Strategic Plan into specific project recommendations. To develop the Statewide Architecture, the project team first inventoried all existing and planned ITS projects in the state. A project architecture was developed for each identified project, and these project architectures were then merged to form the Statewide Architecture. This report describes the background work that set the stage for the architecture, the actual architecture development …

Intelligent Transportation Systems Business Plan For Kentucky (Final Report), Jennifer R. Walton, Joseph D. Crabtree, Monica L. Barrett, Jerry G. Pigman

Kentucky Transportation Center Research Report

This report presents a Business Plan for Intelligent Transportation Systems (ITS) in Kentucky. The purpose of the Business Plan is to define ITS projects that are planned for implementation from 2002 through 2007. The list of projects contained within this document was developed using Kentucky’s ITS Strategic Plan, the ITS National Architecture, and stakeholder input.

There are 21 projects planned for implementation over the next 6 years at a total estimated cost of nearly $80 million. Another five projects will be considered when the Business Plan is updated in two years. These projects cover a wide range of topics including: …