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Articles 1 - 19 of 19

Full-Text Articles in Engineering

Erbium-Doped Silicon Based Leds, Joseph J. Miceli Jan 2000

Erbium-Doped Silicon Based Leds, Joseph J. Miceli

Journal of the Microelectronic Engineering Conference

A preliminary effort in Electroluminescent (EL) device fabrication using erbium-doped silicon based materials at Rochester Institute of Technology’s Microelectronic Engineering Fabrication Facilities was attempted in this study. Field-assisted infiltration would be used to incorporate erbium ions into a porous silicon film. The film would be oxidized and anneal to form and erbium and oxygen rich active layer suitable for light emission. Different erbium anneals (900°C to 1100°C) would be executed and results would be thoroughly examined for any differences in the electrical or luminescent characteristics. No functional devices were fabricated, but proof of erbium activation and excitation ...


Deconfounding The Effects Of Cu And Cr On Perceived Fe Contamination In Si Using An Spv Technique, Steven V. Nagel Jan 2000

Deconfounding The Effects Of Cu And Cr On Perceived Fe Contamination In Si Using An Spv Technique, Steven V. Nagel

Journal of the Microelectronic Engineering Conference

The effects of iron, copper, and chrome on minority carrier diffusion length measurements in p type, boron doped, silicon were investigated using a surface photovoltage (SPV) technique. Attempts were made to reproduce previous results for iron and chrome, metals which form complexes with boron. Also an attempt was made to study the effect that copper contamination would have upon the SPV results. It was found that the iron results were reproducible, FeB could be photodisassociated, and that the chrome contaminated wafers were not effected by the photodisassociation, CrB pairs were not broken. The copper contaminated wafers were found to be ...


Process Development For An Anti-Reflective Micromechanical Modulator, Jason Neidrich Jan 2000

Process Development For An Anti-Reflective Micromechanical Modulator, Jason Neidrich

Journal of the Microelectronic Engineering Conference

The purpose of this Senior Design project is to design and develop the process for an Anti-Reflective Micromechanical Modulator at RIT’s facility, based on AT&T Bell Laboratories presented device, OFC ‘94). The device is fabricated using common semiconductor materials and is used to reflect a laser signal. There are 2 states of operation: the optically ON state, which reflects the signal, and the optically OFF state, which cancels the signal out through destructive interference. A three-layer mask process was designed on RIT’s IC Layout software, the levels being the Active, Metal, and Sacrificial Evacuation areas. The process ...


A Chrome Ar Film For Binary Photomasks, Matthew Lassiter Jan 2000

A Chrome Ar Film For Binary Photomasks, Matthew Lassiter

Journal of the Microelectronic Engineering Conference

A photomask typically consists of a bulk transparent substrate and a thin metallic film with etched pattern on the surface for light absorption. Stray light reflecting off of the top surface of the photomask is especially problematic because it is focused onto the wafer surface, causing unwanted exposure of the photoresist. . Lithographic performance can be significantly improved if this reflection is reduced with an antireflective layer on the top surface of the photomask. There are commercially developed antireflective films for chrome based photomasks. These films were designed to meet certain specifications for optical density and reflectivity. The goal of this ...


Lithographic Process Evaluation By Cd-Sem, Jason L. Burkholder Jan 2000

Lithographic Process Evaluation By Cd-Sem, Jason L. Burkholder

Journal of the Microelectronic Engineering Conference

In lithography employed in IC fabrication, focus and exposure directly determine the printed resist image. Focus and exposure settings may be optimized with a focus exposure matrix (FEM) in which one parameter is varied by column and the other parameter is varied by row. A focus exposure matrix should be measured on a highly accurate and precise metrology tool, such as a CD-SEM. This experiment was performed using a Canon FPA 2000-i1 stepper, an SSI 150 coat/develop track, and a Hitachi S-6780 CD SEM. ProData was used to graphically analyze the numerical data collected on the CD-SEM. Data collected ...


Investigation Of Tantalum Silicon Oxide As An Attenuated Phase Shift Masking Material For 157nm Lithography, Matthew Malley Jan 2000

Investigation Of Tantalum Silicon Oxide As An Attenuated Phase Shift Masking Material For 157nm Lithography, Matthew Malley

Journal of the Microelectronic Engineering Conference

As the microelectronics industry trends toward 157nm lithography and device geometries shrink below O.1μm, it seems more than likely that phase shift masking will be necessary as a means of optical enhancement. The attenuated phase shift mask is an attractive tool by which lithographers hope to push their art to its limits. However, potential niaterials for use as the attenuating film at wavelengths as low as 157nm have yet to be determined. There are several requirements that must be met by a material before it will be considered seriously for use on attenuating phase shift masks. One ...


Effects Of Nitrogen Implantation On Oxide Growth And Quality, Jason E. Meiring Jan 2000

Effects Of Nitrogen Implantation On Oxide Growth And Quality, Jason E. Meiring

Journal of the Microelectronic Engineering Conference

The effects of implanting nitrogen prior to gate oxidation are presented. Three different doses of N+, N2+, and Si+ were implanted, followed by a 20- minute 950°C dry oxide growth. Growth rate, interface quality and breakdown strength were measured. Results show up to a 70% reduction in growth rate for high dose nitrogen implants, but no change for silicon implants. The interface trap density decreased with increasing dose for all three species. Oxides grown over N2+ implanted silicon showed field strengths comparable to standard oxides.


Mosfets With Variable Gate Oxide Thickness By Selective Nitrogen Ion Implantation, Dave Rines Jan 2000

Mosfets With Variable Gate Oxide Thickness By Selective Nitrogen Ion Implantation, Dave Rines

Journal of the Microelectronic Engineering Conference

The incorporation of nitrogen in silicon has been shown to retard the oxidation growth rate. The present study produced aluminum gate PMOSFETs with varied gate oxide thickness on the same chip through selective nitrogen ion implantation. The nitrogen implant dose of 4x1014 ions/cm2 at 35 keV prior to gate oxide growth reduced the oxidation rate between 10% and 60% at the oxidation schedules employed. This active area N-implant led to no degradation in electrical parameters such as gate delay, mobility, or subthreshold swing. MOSFETs with different gate oxide thicknesses allow for different threshold voltages on the same chip ...


Design And Fabrication Of Ring Gate Surface Junction Tunneling Devices, Eliott R. Hughes Jan 2000

Design And Fabrication Of Ring Gate Surface Junction Tunneling Devices, Eliott R. Hughes

Journal of the Microelectronic Engineering Conference

Silicon based ring gate surface junction tunneling devices (SJT) were studied due to their promise of incorporating quantum functional devices with integrated circuits. SJT devices of various gate lengths ranging from 1 μm to 50 μm were designed using Mentor Graphics tools, and were fabricated using standard CMOS processes on S1MOX substrates. SIMOX wafers were used to help reduce bulk leakage and enhance the drain impurity profile. SIMOX mesa isolation also significantly reduced the process flow.


Reactive Sputtering Of Tantalum Nitrides For Diffusion Barrier Layers, Deepa Gazula Jan 2000

Reactive Sputtering Of Tantalum Nitrides For Diffusion Barrier Layers, Deepa Gazula

Journal of the Microelectronic Engineering Conference

The objective of this project is to develop a robust process to deposit Tantalum nitride barrier layer for copper metallization. TaN films were reactively sputtered in a twin cathode AC inverted cylindrical magnetron configuration using the lonTech Cyclone sputtering system. The dependence of thickness, resistivity and phase changes as a function of N2 flow rate was studied. A designed experimental approach was used to optimize resistivity and the phases formed. A 10 sccm N2 flow (with 99 sccm Ar) deposited at 4 mTorr and 2 kW pressure gave an amorphous bcc-phase Ta(N) with a low resistivity of ...


The Effect Of Fluorine On Boron Diffusion, Michele Honan Jan 2000

The Effect Of Fluorine On Boron Diffusion, Michele Honan

Journal of the Microelectronic Engineering Conference

The role of fluorine in a BF2 implant has been investigated by implanting BF2, B alone and different combinations of B and F at equivalent implant energies. Each combination was designed to test for something, such as the effect of fluorine after B was implanted or the F damage before B was implanted. The wafers from each group received a spike anneal at 1075°C. The resulting boron profiles after implant and after spike anneal were obtained by SIMS analysis. Sheet resistance was measured and compared with the values calculated from the profiles. The junctions with boron implant ...


Rit Process And Device Simulation With Microtec, Charles R. Overbeck Jan 2000

Rit Process And Device Simulation With Microtec, Charles R. Overbeck

Journal of the Microelectronic Engineering Conference

Microtec, a diffusion-drift model simulator by Siborg Systems, Inc., was used to simulate RIT’s process for a 2-micron NFET (Long Channel), a scaled down NFET (Short Channel), and our new advanced CMOS Process NFET. The accuracy of the simulator was tested with voltage threshold curves, sub-threshold characteristic tests, potential distribution plots, doping profiles, and oxide growth measurements. Microtec proved to be able to easily model RIT’s device performance and process characteristics with only a small amount of modification.


The Beneficial Effects Of Thin Film Stress In The Fabrication Of A Mems Device, Justin E. Brown Jan 2000

The Beneficial Effects Of Thin Film Stress In The Fabrication Of A Mems Device, Justin E. Brown

Journal of the Microelectronic Engineering Conference

Microelectromechanical systems (MEMS) are playing an increasing role in the semiconductor industry today. The modeling and manufacturing of mechanical devices on a microscopic level have made their way from the area of singularly fabricated devices for research into the bulk processing of the commercial market Many of these commercial devices are of the optical variety. And there has also been successful work done in combining integrated circuits with MEMS. Presented here is a process for the fabrication of an optical device called a microshutter. The device consists of a moveable electrode constructed of a stack of Si02/Al/SiO ...


Investigation Of Silicon Etching Effects For Monolithic Integration Of Mems With Cmos, Matthew J. Daniello Jan 2000

Investigation Of Silicon Etching Effects For Monolithic Integration Of Mems With Cmos, Matthew J. Daniello

Journal of the Microelectronic Engineering Conference

Monolithic integration of CMOS and MEMS is quickly proving to be a viable asset to current complex structures. However, synthesis of these technologies has proven to have multiple processing obstacles. Depending on the method used to create these devices, the hurdles include the effects of silicon etching and high temperature processing. For this experiment, previously processed CMOS wafers were obtained and a trench was etched into the silicon. “Family of curves” plots of the working CMOS wafers were taken before and after processing to study any changes in ID. Results have shown that the processing of this integration will ...


Copper Interconnect Development At Rit, Ashish Kushwaha Jan 2000

Copper Interconnect Development At Rit, Ashish Kushwaha

Journal of the Microelectronic Engineering Conference

Aluminum is the current metal of choice for metallization in the IC industry. However, serious electromigration problems, and inferior thermal stability limit its performance and reliability. Copper is an attractive alternative having higher electrical conductivity and improved electromigration performance compared to Aluminum. However, Cu is a fast diffuser in Si, Si02, and interlevel dielectrics (ILD). To eliminate this issue, a layer of diffusion barrier (DB) material which is conducting, chemically passive with Copper, has good adhesion properties with Cu and ltD and has high thermal stability is required. Damascene process for Cu was utilized to pattern the wafers in this ...


Development Of Lto Lpcvd Process For 6" Wafers At Rit, Karthika Sivagurunathan Jan 2000

Development Of Lto Lpcvd Process For 6" Wafers At Rit, Karthika Sivagurunathan

Journal of the Microelectronic Engineering Conference

Low Temperature Oxide (LTO) thin films were prepared using a Low Pressure Chemical Vapor Deposition process. By employing statistically designed experiments, the number of experimental runs required was minimized. The full-factorial experimental design was set up to examine effects temperature, gas flow and pressure had on deposition rate, wafer to wafer uniformity, within the wafer uniformity and within run uniformity. The average deposition rate found to be 112A per minute. The LTO baseline process conditions optimized based on the results of this project are: Temperature of 410C, pressure of 33OmTorr and gas flow ratio of 0.55.


Tantalum Pentoxide Deposition And Applications, Mark A. Bossard Jan 2000

Tantalum Pentoxide Deposition And Applications, Mark A. Bossard

Journal of the Microelectronic Engineering Conference

A Tantalum Pentoxide deposition by reactive sputtering was optimized on a CVC-601 sputterer and working MOS transistors were made using Tantalum Pentoxide. The target was an 8” pure Tantalum target. The optimization was done over a power range of 700 to 1700W DC and over an Oxygen flow of 15 to 35%. The optimal process from this study was at 1200W and an Oxygen flow of 15% or less. A standard PMOS process was modified to use Tantalum Pentoxide using the gate dielectric. The resulting transistors worked well.


Cobalt Silicide Formation And Patterning Technology, Neil S. Patel Jan 2000

Cobalt Silicide Formation And Patterning Technology, Neil S. Patel

Journal of the Microelectronic Engineering Conference

The goal of this investigation was to develop a cobalt silicide formation process as a stepping stone to investigate a novel patterning technique known as, LOCOSI (LOCal Oxidation of Silicide). Cobalt suicide films were formed by sputter depositing cobalt onto silicon wafers then annealed at temperatures varying from 750 - 1000°C using two methods. The first method was a conventional anneal using a horizontal furnace using a forming gas ambient. The second method was a RTA (Rapid Thermal Anneal) using a nitrogen ambient. The RTA process for silicidation provided essentially a continuous film with minimal cracking, whereas the furnace anneals ...


Development Of An Anisotropic, Selective Polycrystalline Silicon Dry Etch Process, Randy Supczak Jan 2000

Development Of An Anisotropic, Selective Polycrystalline Silicon Dry Etch Process, Randy Supczak

Journal of the Microelectronic Engineering Conference

The development of a polysilicon dry etch process that would result in anisotropic etch profiles as well as high selectivity to photoresist and silicon dioxide has been studied. It was found that decreasing the amount of fluorine (SF6) in the plasma significantly increased the polysilicon etch rate while only increasing the etch rate of silicon dioxide slightly. Two optimal processes were found: One that emphasized anisotropy (70% SF6 flow, 90mTorr pressure, and 200W RF power) and one that emphasized Si02 selectivity (70% SF6 flow, 23OmTorr pressure, and 200W RF power).