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Full-Text Articles in Engineering

Evaluation Of Robust Deep Learning Pipelines Targeting Low Swap Edge Deployment, David Carter Cornett Dec 2021

Evaluation Of Robust Deep Learning Pipelines Targeting Low Swap Edge Deployment, David Carter Cornett

Masters Theses

The deep learning technique of convolutional neural networks (CNNs) has greatly advanced the state-of-the-art for computer vision tasks such as image classification and object detection. These solutions rely on large systems leveraging wattage-hungry GPUs to provide the computational power to achieve such performance. However, the size, weight and power (SWaP) requirements of these conventional GPU-based deep learning systems are not suitable when a solution requires deployment to so called "Edge" environments such as autonomous vehicles, unmanned aerial vehicles (UAVs) and smart security cameras.

The objective of this work is to benchmark FPGA-based alternatives to conventional GPU systems that have the …


High Frequency Injection Sensorless Control For A Permanent Magnet Synchronous Machine Driven By An Fpga Controlled Sic Inverter, Jared Walden Aug 2021

High Frequency Injection Sensorless Control For A Permanent Magnet Synchronous Machine Driven By An Fpga Controlled Sic Inverter, Jared Walden

Masters Theses

As motor drive inverters continue to employ Silicon Carbide (SiC) and Gallium Nitride (GaN) devices for power density improvements, sensorless motor control strategies can be developed with field-programmable gate arrays (FPGA) to take advantage of high inverter switching frequencies. Through the FPGA’s parallel processing capabilities, a high control bandwidth sensorless control algorithm can be employed. Sensorless motor control offers cost reductions through the elimination of mechanical position sensors or more reliable electric drive systems by providing additional position and speed information of the electric motor. Back electromotive force (EMF) estimation or model-based methods used for motor control provide precise sensorless …


Scalable High-Speed Communications For Neuromorphic Systems, Aaron Reed Young Aug 2017

Scalable High-Speed Communications For Neuromorphic Systems, Aaron Reed Young

Masters Theses

Field-programmable gate arrays (FPGA), application-specific integrated circuits (ASIC), and other chip/multi-chip level implementations can be used to implement Dynamic Adaptive Neural Network Arrays (DANNA). In some applications, DANNA interfaces with a traditional computing system to provide neural network configuration information, provide network input, process network outputs, and monitor the state of the network. The present host-to-DANNA network communication setup uses a Cypress USB 3.0 peripheral controller (FX3) to enable host-to-array communication over USB 3.0. This communications setup has to run commands in batches and does not have enough bandwidth to meet the maximum throughput requirements of the DANNA device, resulting …


Modeling And Design Of A Low-Level Rf Control System For The Accumulator Ring At Spallation Neutron Source, Michael G. Trout Aug 2017

Modeling And Design Of A Low-Level Rf Control System For The Accumulator Ring At Spallation Neutron Source, Michael G. Trout

Masters Theses

Since its commissioning in 2006, Spallation Neutron Source (SNS) at Oak Ridge National Laboratory has greatly contributed to the field of neutron science, but some critical systems are reaching end-of-life. This obsolescence must be addressed for the accelerator to continue providing world-class research capabilities. One such system needing redesign is the low-level RF (LLRF) control system for the proton accumulator ring. While this system has performed acceptably for over a decade, it is sparsely documented and robust operational models are unavailable. To ensure the new design meets or exceeds current performance metrics, we analyzed the existing LLRF control system and …


Tiled Danna: Dynamic Adaptive Neural Network Array Scaled Across Multiple Chips, Patricia Jean Eckhart Aug 2017

Tiled Danna: Dynamic Adaptive Neural Network Array Scaled Across Multiple Chips, Patricia Jean Eckhart

Masters Theses

Tiled Dynamic Adaptive Neural Network Array(Tiled DANNA) is a recurrent spiking neural network structure composed of programmable biologically inspired neurons and synapses that scales across multiple FPGA chips. Fire events that occur on and within DANNA initiate spiking behaviors in the programmable elements allowing DANNA to hold memory through the synaptic charge propagation and neuronal charge accumulation. DANNA is a fully digital neuromorphic computing structure based on the NIDA architecture. To support initial prototyping and testing of the Tiled DANNA, multiple Xilinx Virtex 7 690Ts were leveraged. The primary goal of Tiled DANNA is to support scaling of DANNA neural …


Architecture For Real-Time, Low-Swap Embedded Vision Using Fpgas, Steven Andrew Clukey Dec 2016

Architecture For Real-Time, Low-Swap Embedded Vision Using Fpgas, Steven Andrew Clukey

Masters Theses

In this thesis we designed, prototyped, and constructed a printed circuit board for real-time, low size, weight, and power (SWaP) HDMI video processing and developed a general purpose library of image processing functions for FPGAs.

The printed circuit board is a baseboard for a Xilinx Zynq based system-on-module (SoM). The board provides power, HDMI input, and HDMI output to the SoM and enables low-SWaP, high-resolution, real-time video processing.

The image processing library for FPGAs is designed for high performance and high reusability. These objectives are achieved by utilizing the Chisel hardware construction language to create parameterized modules that construct low-level …


A Hardware Based Audio Event Detection System, Jacob Daniel Tobin Dec 2015

A Hardware Based Audio Event Detection System, Jacob Daniel Tobin

Masters Theses

Audio event detection and analysis is an important tool in many fields, from entertainment to security. Recognition technologies are used daily for parsing voice commands, tagging songs, and real time detection of crimes or other undesirable events. The system described in this work is a hardware based application of an audio detection system, implemented on an FPGA. It allows for the detection and characterization of gunshots and other events, such as breaking glass, by comparing a recorded audio sample to 20+ stored fingerprints in real time. Additionally, it has the ability to record flagged events and supports integration with mesh …


Danna A Neuromorphic Computing Vlsi Chip, Christopher Paul Daffron Aug 2015

Danna A Neuromorphic Computing Vlsi Chip, Christopher Paul Daffron

Masters Theses

Dynamic Adaptive Neural Network Arrays (DANNAs) are neuromorphic systems that exhibit spiking behaviors and can be designed using evolutionary optimization. Array elements are rapidly reconfigurable and can function as either neurons or synapses with programmable interconnections and parameters. Currently, DANNAs are implemented using a Field Programmable Gate Array (FPGA) and are constrained by this technology. To alleviate these constraints and introduce new and improved features, a semi-custom Very Large Scale Integration (VLSI) implementation has been created. This implementation improves upon the FPGA implementation in three key areas. The density of the array is improved, with 5,625 elements on a single …


Air: Adaptive Dynamic Precision Iterative Refinement, Jun Kyu Lee Aug 2012

Air: Adaptive Dynamic Precision Iterative Refinement, Jun Kyu Lee

Doctoral Dissertations

In high performance computing, applications often require very accurate solutions while minimizing runtimes and power consumption. Improving the ratio of the number of logic gates implementing floating point arithmetic operations to the total number of logic gates enables greater efficiency, potentially with higher performance and lower power consumption. Software executing on the fixed hardware in Von-Neuman architectures faces limitations on improving this ratio, since processors require extensive supporting logic to fetch and decode instructions while employing arithmetic units with statically defined precision. This dissertation explores novel approaches to improve computing architectures for linear system applications not only by designing application-specific …


A Memory Controller For Fpga Applications, Bryan Jacob Hunter Aug 2012

A Memory Controller For Fpga Applications, Bryan Jacob Hunter

Masters Theses

As designers and researchers strive to achieve higher performance, field-programmable gate arrays (FPGAs) become an increasingly attractive solution. As coprocessors, FPGAs can provide application specific acceleration that cannot be matched by modern processors. Most of these applications will make use of large data sets, so achieving acceleration will require a capable interface to this data. The research in this thesis describes the design of a memory controller that is both efficient and flexible for FPGA applications requiring floating point operations. In particular, the benefits of certain design choices are explored, including: scalability, memory caching, and configurable precision. Results are given …


Design, Implementation, And Analysis Of A Time Of Arrival Measurement System For Rotating Machinery, Bryan Will Hayes May 2012

Design, Implementation, And Analysis Of A Time Of Arrival Measurement System For Rotating Machinery, Bryan Will Hayes

Masters Theses

The Non-contact Stress Measurement System (NSMS) acquires critical time of arrival data from multiple optical probes viewing a rotating piece of machinery, such as blades on a turbine engine rotor. The signal from each probe must be converted from light energy to an electrical signal, conditioned, and timed by a high speed counter to measure the time of arrival of the rotating machinery. This thesis describes, in detail, the design and analysis of the photo-detector electronics, analog signal conditioning electronics, and the timing electronics utilized in measuring the time of arrival. To measure the time of arrival with precision, the …


Turbo Bayesian Compressed Sensing, Depeng Yang Aug 2011

Turbo Bayesian Compressed Sensing, Depeng Yang

Doctoral Dissertations

Compressed sensing (CS) theory specifies a new signal acquisition approach, potentially allowing the acquisition of signals at a much lower data rate than the Nyquist sampling rate. In CS, the signal is not directly acquired but reconstructed from a few measurements. One of the key problems in CS is how to recover the original signal from measurements in the presence of noise. This dissertation addresses signal reconstruction problems in CS. First, a feedback structure and signal recovery algorithm, orthogonal pruning pursuit (OPP), is proposed to exploit the prior knowledge to reconstruct the signal in the noise-free situation. To handle the …


An Fpga Based Implementation Of The Exact Stochastic Simulation Algorithm, Phani Bharadwaj Vanguri Dec 2010

An Fpga Based Implementation Of The Exact Stochastic Simulation Algorithm, Phani Bharadwaj Vanguri

Masters Theses

Mathematical and statistical modeling of biological systems is a desired goal for many years. Many biochemical models are often evaluated using a deterministic approach, which uses differential equations to describe the chemical interactions. However, such an approach is inaccurate for small species populations as it neglects the discrete representation of population values, presents the possibility of negative populations, and does not represent the stochastic nature of biochemical systems. The Stochastic Simulation Algorithm (SSA) developed by Gillespie is able to properly account for these inherent noise fluctuations. Due to the stochastic nature of the Monte Carlo simulations, large numbers of simulations …