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FPGA

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Full-Text Articles in Engineering

Adaptive-Hybrid Redundancy For Radiation Hardening, Nicolas S. Hamilton Sep 2019

Adaptive-Hybrid Redundancy For Radiation Hardening, Nicolas S. Hamilton

Theses and Dissertations

An Adaptive-Hybrid Redundancy (AHR) mitigation strategy is proposed to mitigate the effects of Single Event Upset (SEU) and Single Event Transient (SET) radiation effects. AHR is adaptive because it switches between Triple Modular Redundancy (TMR) and Temporal Software Redundancy (TSR). AHR is hybrid because it uses hardware and software redundancy. AHR is demonstrated to run faster than TSR and use less energy than TMR. Furthermore, AHR allows space vehicle designers, mission planners, and operators the flexibility to determine how much time is spent in TMR and TSR. TMR mode provides faster processing at the expense of greater energy usage. TSR ...


Statistical Analysis Of A Channel Emulator For Noisy Gradient Descent Low Density Parity Check Decoder, Rakin Muhammad Shadab Aug 2019

Statistical Analysis Of A Channel Emulator For Noisy Gradient Descent Low Density Parity Check Decoder, Rakin Muhammad Shadab

All Graduate Theses and Dissertations

The purpose of a channel emulator is to emulate a communication channel in real-life use case scenario. These emulators are often used in the domains of research in digital and wireless communication. One such area is error correction coding, where transmitted data bits over a channel are decoded and corrected to prevent data loss. A channel emulator that does not follow the properties of the channel it is intended to replicate can lead to mistakes while analyzing the performance of an error-correcting decoder. Hence, it is crucial to validate an emulator for a particular communication channel. This work delves into ...


An Fpga Implementation Of Digital Guitar Effects, Carson James Robles Jun 2019

An Fpga Implementation Of Digital Guitar Effects, Carson James Robles

Computer Engineering

One of the most versatile aspects of the electric guitar is its ability to change its sound completely and on-the-fly through the use of effects pedals. Conventional guitar pedals contain one effect and can be chained together. The goal of this project is to serve as a contained multi-effects station with five popular electric guitar effects packed into one product. On top of this, the effects each have two tunable parameters to allow users to dial in the exact tone they are looking for. All of the signal processing done in this project is conducted on an FPGA which also ...


Surface Engineering Solutions For Immersion Phase Change Cooling Of Electronics, Brendon M. Doran May 2019

Surface Engineering Solutions For Immersion Phase Change Cooling Of Electronics, Brendon M. Doran

Master's Theses

Micro- and nano-scale surface modifications have been a subject of great interest for enhancing the pool boiling heat transfer performance of immersion cooling systems due to their ability to augment surface area, improve wickability, and increase nucleation site density. However, many of the surface modification technologies that have been previously demonstrated show a lack of evidence concerning scalability for use at an industrial level. In this work, the pool boiling heat transfer performance of nanoporous anodic aluminum oxide (AAO) films, copper oxide (CuO) nanostructure coatings, and 1D roll-molded microfin arrays has been studied. Each of these technologies possess scalability in ...


Digital Implementation Of Bio-Inspired Spiking Neuronal Networks, Shaghayegh Gomar Mar 2019

Digital Implementation Of Bio-Inspired Spiking Neuronal Networks, Shaghayegh Gomar

Electronic Theses and Dissertations

Spiking Neural Network as the third generation of artificial neural networks offers a promising solution for future computing, prosthesis, robotic and image processing applications. This thesis introduces digital designs and implementations of building blocks of a Spiking Neural Networks (SNNs) including neurons, learning rule, and small networks of neurons in the form of a Central Pattern Generator (CPG) which can be used as a module in control part of a bio-inspired robot. The circuits have been developed using Verilog Hardware Description Language (VHDL) and simulated through Modelsim and compiled and synthesised by Altera Qurtus Prime software for FPGA devices. Astrocyte ...


Neutron Beam Testing Methodology And Results For A Complex Programmable Multiprocessor Soc, Jordan Daniel Anderson Mar 2019

Neutron Beam Testing Methodology And Results For A Complex Programmable Multiprocessor Soc, Jordan Daniel Anderson

Theses and Dissertations

The Xilinx Multiprocessor System-on-Chip (MPSoC) is a complex device that uses 16nm FinFET technology to combine multiple processors, a large amount of FPGA resources, and many I/O interfaces on a single chip die. These features make the MPSoC a high-performance and architecturally flexible device. The potential computing power makes the MPSoC ideal for many embedded applications including terrestrial and space applications. The MPSoC, however, does not have extensive radiation history as many other devices have. The extent of the effect that ionized particles may have on the MPSoC is not well established. To solve this problem, neutron radiation testing ...


Analyzing Energy Savings In An Fpga Video Processing System Using Dynamic Partial Reconfiguration, Robert Cole Wernsman Jan 2019

Analyzing Energy Savings In An Fpga Video Processing System Using Dynamic Partial Reconfiguration, Robert Cole Wernsman

Graduate Theses and Dissertations

Dynamic Partial Reconfiguration (DPR) can be a useful tool for maximizing FPGA performance while minimizing power consumption and FPGA size requirements. This work explores the application of the DPR technique in a computer vision application that implements two different edge detection algorithms (FASTX and Sobel). This technique could allow for a similar computer vision system to be realized on a smaller, low-power chipset. Different algorithms can have unique characteristics that yield better performance in certain scenarios; the best algorithm for the current scenario may change during runtime. However, implementing all available algorithms in hardware increases the space and power requirements ...


Accelerating Reverse Engineering Image Processing Using Fpga, Matthew Joshua Harris Jan 2019

Accelerating Reverse Engineering Image Processing Using Fpga, Matthew Joshua Harris

Browse all Theses and Dissertations

In recent decades, field programmable gate arrays (FPGAs) have evolved beyond simple, expensive computational components with minimal computing power to complex, inexpensive computational engines. Today, FPGAs can perform algorithmically complex problems with improved performance compared to sequential CPUs by taking advantage of parallelization. This concept can be readily applied to the computationally dense field of image manipulation and analysis. Processed on a standard CPU, image manipulation suffers with large image sets processed by highly sequential algorithms, but by carefully adhering to data dependencies, parallelized FPGA functions or kernels offer the possibility of significant improvement through threaded CPU functions. This thesis ...


Efficient Machine Learning: Models And Accelerations, Zhe Li Dec 2018

Efficient Machine Learning: Models And Accelerations, Zhe Li

Dissertations - ALL

One of the key enablers of the recent unprecedented success of machine learning is the adoption of very large models. Modern machine learning models typically consist of multiple cascaded layers such as deep neural networks, and at least millions to hundreds of millions of parameters (i.e., weights) for the entire model. The larger-scale model tend to enable the extraction of more complex high-level features, and therefore, lead to a significant improvement of the overall accuracy. On the other side, the layered deep structure and large model sizes also demand to increase computational capability and memory requirements. In order to ...


Acoustic Source Localization With A Vtol Suav Deployable Module, Kory Olney Nov 2018

Acoustic Source Localization With A Vtol Suav Deployable Module, Kory Olney

Graduate Theses and Dissertations

A real time acoustic direction-finding module has been developed to estimate the ele- vation and azimuth of an impulsive event while function aboard a small unmanned air- craft vehicle. The generalized cross-correlation with phase transform method was used to estimate time differences of arrival in an 8 channel microphone array. A linear least squares approach was used to calculate an estimate for the direction of arrival. In order to accomplish this task, a vertical takeoff and landing small unmanned aircraft system was assembled to host the direction finding module. The module itself is made up of an eight-channel synchronous analog-to-digital ...


A Basic, Four Logic Cluster, Disjoint Switch Connected Fpga Architecture, Joseph Prachar Jun 2018

A Basic, Four Logic Cluster, Disjoint Switch Connected Fpga Architecture, Joseph Prachar

Computer Engineering

This paper seeks to describe the process of developing a new FPGA architecture from nothing, both in terms of knowledge about FPGAs and in initial design material. Specifically, this project set out to design an FPGA architecture which can implement a simple state machine type design with 10 inputs, 10 outputs and 10 states. The open source Verilog-to-Routing FPGA CAD flow tool was used in order to synthesize, place, and route HDL files onto the architecture. This project was completed in terms of the spirit of the original goals of implementing an FPGA from scratch. Although, the project resulted in ...


Efficient Fpga Soc Processing Design For A Small Uav Radar, Luke Oliver Newmeyer Apr 2018

Efficient Fpga Soc Processing Design For A Small Uav Radar, Luke Oliver Newmeyer

Theses and Dissertations

Modern radar technology relies heavily on digital signal processing. As radar technology pushes the boundaries of miniaturization, computational systems must be developed to support the processing demand. One particular application for small radar technology is in modern drone systems. Many drone applications are currently inhibited by safety concerns of autonomous vehicles navigating shared airspace. Research in radar based Detect and Avoid (DAA) attempts to address these concerns by using radar to detect nearby aircraft and choosing an alternative flight path. Implementation of radar on small Unmanned Air Vehicles (UAV), however, requires a lightweight and power efficient design. Likewise, the radar ...


Efficient Fpga Soc Processing Design For A Small Uav Radar, Luke Oliver Newmeyer Apr 2018

Efficient Fpga Soc Processing Design For A Small Uav Radar, Luke Oliver Newmeyer

Theses and Dissertations

Modern radar technology relies heavily on digital signal processing. As radar technology pushes the boundaries of miniaturization, computational systems must be developed to support the processing demand. One particular application for small radar technology is in modern drone systems. Many drone applications are currently inhibited by safety concerns of autonomous vehicles navigating shared airspace. Research in radar based Detect and Avoid (DAA) attempts to address these concerns by using radar to detect nearby aircraft and choosing an alternative flight path. Implementation of radar on small Unmanned Air Vehicles (UAV), however, requires a lightweight and power efficient design. Likewise, the radar ...


Progressive Network Deployment, Performance, And Control With Software-Defined Networking, Daniel J. Casey Mar 2018

Progressive Network Deployment, Performance, And Control With Software-Defined Networking, Daniel J. Casey

Theses and Dissertations

The inflexible nature of traditional computer networks has led to tightly-integrated systems that are inherently difficult to manage and secure. New designs move low-level network control into software creating software-defined networks (SDN). Augmenting an existing network with these enhancements can be expensive and complex. This research investigates solutions to these problems. It is hypothesized that an add-on device, or "shim" could be used to make a traditional switch behave as an OpenFlow SDN switch while maintaining reasonable performance. A design prototype is found to cause approximately 1.5% reduction in throughput for one ow and less than double increase in ...


Acceleration Of K-Nearest Neighbor And Srad Algorithms Using Intel Fpga Sdk For Opencl, Liyuan Liu Mar 2018

Acceleration Of K-Nearest Neighbor And Srad Algorithms Using Intel Fpga Sdk For Opencl, Liyuan Liu

Electronic Theses and Dissertations

Field Programmable Gate Arrays (FPGAs) have been widely used for accelerating machine learning algorithms. However, the high design cost and time for implementing FPGA-based accelerators using traditional HDL-based design methodologies has discouraged users from designing FPGA-based accelerators. In recent years, a new CAD tool called Intel FPGA SDK for OpenCL (IFSO) allowed fast and efficient design of FPGA-based hardware accelerators from high level specification such as OpenCL. Even software engineers with basic hardware design knowledge could design FPGA-based accelerators. In this thesis, IFSO has been used to explore acceleration of k-Nearest-Neighbour (kNN) algorithm and Speckle Reducing Anisotropic Diffusion (SRAD) simulation ...


Towards Tools For Achieving Third-Party Ip Assurance, Sean Talbot Jensen Mar 2018

Towards Tools For Achieving Third-Party Ip Assurance, Sean Talbot Jensen

Theses and Dissertations

Intellectual Property (IP) is used to speed up the design process and save money. The use of IP and complex CAD tools reduce visibility into the design and what is actually happening during synthesis and implementation. All of the complexity makes it easier for an attacker to insert malicious logic or tamper with the design in ways that are difficult to detect. Not very much work has been done towards the creation of tools to facilitate the safe use of 3rd-party IP. This work presents Physical and Functional Assurance, two approaches that aim to accomplish this task through physically and ...


A Flexible Fpga-Assisted Framework For Remote Attestation Of Internet Connected Embedded Devices, Jared Russell Patten Mar 2018

A Flexible Fpga-Assisted Framework For Remote Attestation Of Internet Connected Embedded Devices, Jared Russell Patten

Theses and Dissertations

Embedded devices permeate our every day lives. They exist in our vehicles, traffic lights, medical equipment, and infrastructure controls. In many cases, improper functionality of these devices can present a physical danger to their users, data or financial loss, etc. Improper functionality can be a result of software or hardware bugs, but now more than ever, is often the result of malicious compromise and tampering, or as it is known colloquially "hacking". We are beginning to witness a proliferation of cyber-crime, and as more devices are built with internet connectivity (in the so called "Internet of Things"), security should be ...


Analysis Of High Performance Scientific Programming Workflows, Withana Kankanamalage Umayanganie Klaassen Jan 2018

Analysis Of High Performance Scientific Programming Workflows, Withana Kankanamalage Umayanganie Klaassen

Open Access Theses & Dissertations

Substantial time is spent on building, optimizing and maintaining large-scale software that is run on supercomputers. However, little has been done to utilize overall resources efficiently when it comes to including expensive human resources. The community is beginning to acknowledge that optimizing the hardware performance such as speed and memory bottlenecks contributes less to the overall productivity than does the development lifecycle of high-performance scientific applications. Researchers are beginning to look at overall scientific workflows for high performance computing. Scientific programming productivity is measured by time and effort required to develop, configure, and maintain a simulation experiment and its constituent ...


An Fpga-Based Hardware Accelerator For Iris Segmentation, Joseph Avey Jan 2018

An Fpga-Based Hardware Accelerator For Iris Segmentation, Joseph Avey

Graduate Theses and Dissertations

Biometric authentication is becoming an increasingly prevalent way to identify a person based on unique physical traits such as the fingerprint, the face, and/or the iris. The iris stands out particularly among these traits due to its relative invariability with time and high uniqueness. However, iris recognition without special, dedicated tools like near-infrared (NIR) cameras and stationary high-performance computers is a challenge. Solutions have been proposed to target mobile platforms like smart phones and tablets by making use of the RGB camera commonly found on those platforms. These solutions tend to be slower than the former due to the ...


Vhdl Auto-Generation Tool For Optimized Hardware Acceleration Of Convolutional Neural Networks On Fpga (Vgt), Muhammad K A Hamdan Jan 2018

Vhdl Auto-Generation Tool For Optimized Hardware Acceleration Of Convolutional Neural Networks On Fpga (Vgt), Muhammad K A Hamdan

Graduate Theses and Dissertations

Convolutional Neural Network (CNN), a popular machine learning algorithm, has been proven as a highly accurate and effective algorithm that has been used in a variety of applications such as handwriting digit recognition, visual recognition, and image classification. State-of-the-art CNNs are computationally intensive, yet their parallel and modular nature make platforms like Field Programmable Gate Arrays (FPGAs) well suited for the acceleration process. Typically, Convolutional Neural Networks take a very long development round to be implemented or accelerated using FPGAs, hence in this thesis, we propose a VHDL generation tool (VGT), which through VHDL code (CNN architecture) can be on ...


Fpga-Based Ir Localization Sensor, Samuel I. Susanto Jan 2018

Fpga-Based Ir Localization Sensor, Samuel I. Susanto

Browse all Theses and Dissertations

Pursuit-evasion scenarios are common in both natural and man-made systems. Often times, the pursuer and evader maneuver in response to each others actions using relative information based on the geometry of the agents and potential obstacles within the environment. The pursuer needs the target's bearing angle in order to plan a trajectory or path to capture it. We propose an FPGA-based infrared sensor array to detect up to 6 agents' bearing angles simultaneously. The final output of the sensor is the bearing angle of other agents. The sensor was tested and validated experimentally. Implementing the sensor and transmitter pair ...


A Proposed Approach To Hybrid Software-Hardware Application Design For Enhanced Application Performance, Alex Shipman Jan 2018

A Proposed Approach To Hybrid Software-Hardware Application Design For Enhanced Application Performance, Alex Shipman

Theses and Dissertations

One important aspect of many commercial computer systems is their performance; therefore, system designers seek to improve the performance next-generation systems with respect to previous generations. This could mean improved computational performance, reduced power consumption leading to better battery life in mobile devices, smaller form factors, or improvements in many areas. In terms of increased system speed and computation performance, processor manufacturers have been able to increase the clock frequency of processors up to a point, but now it is more common to seek performance gains through increased parallelism (such as a processor having more processor cores on a single ...


On-Chip Communication And Security In Fpgas, Shivukumar Basanagouda Patil Jan 2018

On-Chip Communication And Security In Fpgas, Shivukumar Basanagouda Patil

Masters Theses

Innovations in Field Programmable Gate Array (FPGA) manufacturing processes and architectural design have led to the development of extremely large FPGAs. There has also been a widespread adaptation of these large FPGAs in cloud infrastructures and data centers to accelerate search and machine learning applications. Two important topics related to FPGAs are addressed in this work: on-chip communication and security. On-chip communication is quickly becoming a bottleneck in to- day’s large multi-million gate FPGAs. Hard Networks-on-Chip (NoC), made of fixed silicon, have been shown to provide low power, high speed, flexible on-chip communication. An iterative algorithm for routing pre-scheduled ...


Modeling And Design Of A Low-Level Rf Control System For The Accumulator Ring At Spallation Neutron Source, Michael G. Trout Aug 2017

Modeling And Design Of A Low-Level Rf Control System For The Accumulator Ring At Spallation Neutron Source, Michael G. Trout

Masters Theses

Since its commissioning in 2006, Spallation Neutron Source (SNS) at Oak Ridge National Laboratory has greatly contributed to the field of neutron science, but some critical systems are reaching end-of-life. This obsolescence must be addressed for the accelerator to continue providing world-class research capabilities. One such system needing redesign is the low-level RF (LLRF) control system for the proton accumulator ring. While this system has performed acceptably for over a decade, it is sparsely documented and robust operational models are unavailable. To ensure the new design meets or exceeds current performance metrics, we analyzed the existing LLRF control system and ...


Scalable High-Speed Communications For Neuromorphic Systems, Aaron Reed Young Aug 2017

Scalable High-Speed Communications For Neuromorphic Systems, Aaron Reed Young

Masters Theses

Field-programmable gate arrays (FPGA), application-specific integrated circuits (ASIC), and other chip/multi-chip level implementations can be used to implement Dynamic Adaptive Neural Network Arrays (DANNA). In some applications, DANNA interfaces with a traditional computing system to provide neural network configuration information, provide network input, process network outputs, and monitor the state of the network. The present host-to-DANNA network communication setup uses a Cypress USB 3.0 peripheral controller (FX3) to enable host-to-array communication over USB 3.0. This communications setup has to run commands in batches and does not have enough bandwidth to meet the maximum throughput requirements of the ...


Tiled Danna: Dynamic Adaptive Neural Network Array Scaled Across Multiple Chips, Patricia Jean Eckhart Aug 2017

Tiled Danna: Dynamic Adaptive Neural Network Array Scaled Across Multiple Chips, Patricia Jean Eckhart

Masters Theses

Tiled Dynamic Adaptive Neural Network Array(Tiled DANNA) is a recurrent spiking neural network structure composed of programmable biologically inspired neurons and synapses that scales across multiple FPGA chips. Fire events that occur on and within DANNA initiate spiking behaviors in the programmable elements allowing DANNA to hold memory through the synaptic charge propagation and neuronal charge accumulation. DANNA is a fully digital neuromorphic computing structure based on the NIDA architecture. To support initial prototyping and testing of the Tiled DANNA, multiple Xilinx Virtex 7 690Ts were leveraged. The primary goal of Tiled DANNA is to support scaling of DANNA ...


Academic Packing For Commercial Fpga Architectures, Travis D. Haroldsen Jul 2017

Academic Packing For Commercial Fpga Architectures, Travis D. Haroldsen

Theses and Dissertations

With a few exceptions, academic packing algorithms for FPGAs are typically applied solely to theoretical architectures. This has allowed the algorithms to focus on the basic components of packing while abstracting away many of the details dictated by real hardware. As commercially available FPGAs have advanced, however, the academic algorithms and architectures have diverged significantly from their commercial counterparts. In this dissertation, the RapidSmith 2 framework is presented. This framework accurately reflects the architecture of Xilinx FPGAs and provides support for integrating custom tools into the commercial CAD tools. Using this framework, the RSVPack packing algorithm is implemented. The RSVPack ...


Vivado Design Interface: Enabling Cad-Tool Design For Next Generation Xilinx Fpga Devices, Thomas James Townsend Jul 2017

Vivado Design Interface: Enabling Cad-Tool Design For Next Generation Xilinx Fpga Devices, Thomas James Townsend

Theses and Dissertations

The popularity of field-programmable gate arrays (FPGA) has grown in recent years due to their potential performance advantages over sequential software, and as a prototyping platform for application-specific integrated circuits (ASIC). Vendors such as Xilinx offer automated tool suites that can be used to program FPGAs based on a RTL description. These tool suites are sufficient forgeneral users, but they usually don't provide the opportunity to integrate custom computer-aideddesign (CAD) tools into the regular design flow. Xilinx first offered this capability in their ISE tool suite with the Xilinx Design Language (XDL). Using XDL, a Xilinx design could be ...


General-Purpose Digital Filter Platform, Michael Cheng Jun 2017

General-Purpose Digital Filter Platform, Michael Cheng

Electrical Engineering

This senior project provides a platform for high-speed, general-purpose digital filter implementation. EE 459 currently implements digital filters using reprogrammable digital signal processor boards. These aging digital signal processors serially calculate each difference equation term. Operating at 1 Mega-sample per second, the new general-purpose platform simultaneously processes at least ten digital filtering difference equation coefficients. The platform also features an audio jack input and BNC connectors for viewing input and output signals. The filter digitizes single channel audio signals at 44.1 kHz sampling rate with 16-bit precision or 1 MHz sampling at 8-bit precision. The new reprogrammable platform includes ...


Embedded Processors On Fpga: Hard-Core Vs Soft-Core, Vivek J. Vazhoth Kanhiroth May 2017

Embedded Processors On Fpga: Hard-Core Vs Soft-Core, Vivek J. Vazhoth Kanhiroth

Masters Theses

Field Programmable Gate Arrays (FPGAs) are integrated circuits (ICs) that can be reprogrammed by the consumer after manufacturing. They are based on a matrix of configurable logic blocks connected via programmable interconnects that enables the designer to quickly recreate hardware circuits. In the past, FPGAs were primarily used for prototyping and debugging purposes. However, with their increased popularity, many commercial products now incorporate FPGAs.

In the late 1990s, FPGA vendors introduced System-on-chip (SoC) devices that housed one or more hard-core processors and an FPGA fabric on a single IC to allow for more complex designs that involved hardware and software ...