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Full-Text Articles in Engineering
Development Of A Bilayer Metallization For Rit's Existing Cmos Process, Anthony Nguyen
Development Of A Bilayer Metallization For Rit's Existing Cmos Process, Anthony Nguyen
Journal of the Microelectronic Engineering Conference
The design and fabrication of a two-level subtractive aluminum metal backend was completed at the Rochester Institute of Technology. Metall-Metal2 (M1-M2) via chains were used as electrical test structures and tested operational. The optimal process uses 4000A of LTO for an ILD, a non-heated metal2 aluminum sputter deposition, and a chlorine-based plasma for metal etch. Resistance measurements taken through via chains produced values of —400Ω. While an ideal aluminum bar of the via chain’s dimensions should have a resistance of —100Ω, a contact resistance exists at each via throughout the chain and increases the resistance value. Capacitors were also electrically …
Process Design, Development, Fabrication And Verification Of A Cmos Technology For Rit, Jeremiah L. Hebding
Process Design, Development, Fabrication And Verification Of A Cmos Technology For Rit, Jeremiah L. Hebding
Journal of the Microelectronic Engineering Conference
The motivation in creation of the Strongarm process flow was to create a robust “enabling” process that was easy to manufacture. Optimum process conditions have been determined through extensive SUPREM simulation. Electrical examination using ATLAS software allowed for parameter extraction of the computer-generated devices. Modeling the extracted parameters with standard device physics equations allowed for a SPICE level-2 analysis that could be verified through electrical testing of actual fabricated devices. The technology was designed for a two micron, twin-well process incorporating a 4Onm gate oxide and an N+ poly gate. Source and drain implants are at 2E15 cm2, …
Moving Rit To Submicron Technology: Fabrication Of 0.5Μm P-Channel Mos Transistors, Lisa M. Camp
Moving Rit To Submicron Technology: Fabrication Of 0.5Μm P-Channel Mos Transistors, Lisa M. Camp
Journal of the Microelectronic Engineering Conference
In this investigation, efforts have been made to move the Microelectronic Engineering Program at Rochester Institute of Technology to the next technology node by developing and fabricating a 0.5μm PMOS process. Currently, RIT is fabricating 1.0μm CMOS devices. A successful 0.5μm PMOS process can be incorporated into a full flow 0.5μm CMOS process. Both process and electrical simulations were done in order to predict performance. Key process features include blanket n-well, LOCOS isolation, 15nm gate oxide, i-line lithography, self-aligned source and drain, P+ doped polysilicon gates, and shallow source and drains. A test chip was created and the fabrication process …
Low Energy Ion Implant Capabilities At Rit, Brian J. Miga
Low Energy Ion Implant Capabilities At Rit, Brian J. Miga
Journal of the Microelectronic Engineering Conference
With the ever-decreasing size of device geometries today, all aspects of processing must allow for proper scaling of device parameters including junction depths. Currently in industry this challenge is met with ultra-low-energy ion implants combined with rapid thermal annealing to create the necessary profiles. It is also important to have good uniformity and throughput in order for the process to be acceptable in a manufacturing environment. Since the installation of RIT’s Varian 350D last year, there have been no implants performed at less than 3OKeV. In order to develop future processes for the student-run factory and open research possibilities, ion …
Full-Wafer Dmos Fabrication At Rit, Stephen Sudirgo, Alex Pamatat
Full-Wafer Dmos Fabrication At Rit, Stephen Sudirgo, Alex Pamatat
Journal of the Microelectronic Engineering Conference
A well understanding of basic structure of Double Diffused Metal Oxide Semiconductor (DMOS) and the concept of segmented large capacitor creates possibility to produce a full-wafer DMOS. Using the Mylar Mask Technology, the final metal layer can be patterned accordingly so that to leave out any damaged fragments. Thus, it will increase the possibility of higher yield. Most of the basic fabrication processes will be done at RIT microelectronics lab facilities, and the functionality tests will be conducted at Naval Research Lab. Therefore, this paper is intended to give a general overview of concepts involved and the fabrication processes.
Rit Process And Device Simulation With Microtec, Charles R. Overbeck
Rit Process And Device Simulation With Microtec, Charles R. Overbeck
Journal of the Microelectronic Engineering Conference
Microtec, a diffusion-drift model simulator by Siborg Systems, Inc., was used to simulate RIT’s process for a 2-micron NFET (Long Channel), a scaled down NFET (Short Channel), and our new advanced CMOS Process NFET. The accuracy of the simulator was tested with voltage threshold curves, sub-threshold characteristic tests, potential distribution plots, doping profiles, and oxide growth measurements. Microtec proved to be able to easily model RIT’s device performance and process characteristics with only a small amount of modification.
Copper Interconnect Development At Rit, Ashish Kushwaha
Copper Interconnect Development At Rit, Ashish Kushwaha
Journal of the Microelectronic Engineering Conference
Aluminum is the current metal of choice for metallization in the IC industry. However, serious electromigration problems, and inferior thermal stability limit its performance and reliability. Copper is an attractive alternative having higher electrical conductivity and improved electromigration performance compared to Aluminum. However, Cu is a fast diffuser in Si, Si02, and interlevel dielectrics (ILD). To eliminate this issue, a layer of diffusion barrier (DB) material which is conducting, chemically passive with Copper, has good adhesion properties with Cu and ltD and has high thermal stability is required. Damascene process for Cu was utilized to pattern the wafers in this …
Development Of Lto Lpcvd Process For 6" Wafers At Rit, Karthika Sivagurunathan
Development Of Lto Lpcvd Process For 6" Wafers At Rit, Karthika Sivagurunathan
Journal of the Microelectronic Engineering Conference
Low Temperature Oxide (LTO) thin films were prepared using a Low Pressure Chemical Vapor Deposition process. By employing statistically designed experiments, the number of experimental runs required was minimized. The full-factorial experimental design was set up to examine effects temperature, gas flow and pressure had on deposition rate, wafer to wafer uniformity, within the wafer uniformity and within run uniformity. The average deposition rate found to be 112A per minute. The LTO baseline process conditions optimized based on the results of this project are: Temperature of 410C, pressure of 33OmTorr and gas flow ratio of 0.55.
Critical Dimension Analysis On The Rit Canon I-Line Stepper, Justin Novak
Critical Dimension Analysis On The Rit Canon I-Line Stepper, Justin Novak
Journal of the Microelectronic Engineering Conference
This project involved the simulation and analysis of critical dimensions (CD) using the RIT Canon 2000i1 i-line stepper. This was accomplished by optimizing the stepper parameters for specific resist feature widths. There are many tools and methods that lithography engineers have at their disposal for use in optimizing current and future lithography processes. The focus-exposure (1?~E) matrix and resulting plot are integral parts of standard IC processing~ It is one of the most important plots used in lithography since it demonstrates how exposure and focus work together to affect critical dimension, sidewall angle, and resist thickness loss data. This data …
Preparation Of Rit For 157-Nm Lithography, Brian Lee Porter
Preparation Of Rit For 157-Nm Lithography, Brian Lee Porter
Journal of the Microelectronic Engineering Conference
This project investigated the feasibility of 157-nm Vacuum UltraViolet (VUV) Lithography and its’ possible utilization as a future source to extend the capabilities of optical lithography. In addition, this project undertook the initialization of VUV lithography here at JUT by the conversion of a 193-nm ArF excimer laser to a 157-nm F2 excimer laser source. The investigation of the completed body of work on 157-nm lithography led to the conclusion that this technology is viable and may represent the last frontier with respect to optical lithography. The excimer laser at RIT was successfully retrofitted for 157-nm operation and exhibited RIT’s …
The Design Of An Inorganic Barc, Andrew Veter
The Design Of An Inorganic Barc, Andrew Veter
Journal of the Microelectronic Engineering Conference
A methodology was arrived at for the design of an inorganic bottom antireflective coating (BARC). The design methodology consisted of four parts. First, a material compatible with IC processing was chosen. Second, simulation was performed to determine the optimum optical properties of the material, where the materials extinction coefficient, and film thickness were varied to produce zero substrate reflectivity. Third, the stochiometry of the material was varied through experimentation to produce a film with the index of refraction and extinction coefficient as close as possible to the simulation results. Fourth, the results of step three were used in simulation to …
Calibration Of Process And Electrical Models For Rit Vertical Npn Bipolar Junction Transistors, Lena Zavyalova
Calibration Of Process And Electrical Models For Rit Vertical Npn Bipolar Junction Transistors, Lena Zavyalova
Journal of the Microelectronic Engineering Conference
Presented study is based on the need in 2D process and device simulations providing a good estimation of in-line process and electrical parameters for RIT vertical NPN bipolar junction transistors. These involve process and electrical modeling adjustments in order to reproduce vertical dopant profiles and show an appropriate electrical behavior of simulated BJTs Technology Modeling Associates (TMA) software has been implemented to facilitate this task. Theoretical and experimental verification efforts have been performed to examine the validity of the simulation results, and good agreement has been obtained.
Formation Of Sidewall Spacers And Titanium Salicide For Rit's Sub-Micron Cmos, S K. Bhaskaran
Formation Of Sidewall Spacers And Titanium Salicide For Rit's Sub-Micron Cmos, S K. Bhaskaran
Journal of the Microelectronic Engineering Conference
Low Temperature Oxide (LTO) sidewall spacers have been successfully fabricated using etchback an technique. The process for forming these features was optimised for repeatibility for RIT's sub-micron CMOS. In addition, a reliable process for forming low resistive self aligning titanium silicide was also developed using these sidewall spacers.
Design And Fabrication Of Five Microns Nmos Sram, Robert Chizmadia
Design And Fabrication Of Five Microns Nmos Sram, Robert Chizmadia
Journal of the Microelectronic Engineering Conference
A 126 bit by one bit NMDS static RAM was designed following design rules for RIT’s standard four layer NMDS process. Verification of working devices was done using the SPICE circuit simulator, but some concerns exist with this because of assumptions made in model parameters. Fabrication was an intended goal of this project, but time restraints allowed only masks to be made.
Bicmos Vs Cmos At Rit, Anatole Raif
Bicmos Vs Cmos At Rit, Anatole Raif
Journal of the Microelectronic Engineering Conference
This project involved the performance comparison of the standard RIT N-well CMOS and a proposed BiCMOS processes. Device parameters were extracted from TMA SUPREM-3 simulations and used to create NPN, PMOS, and NMOS model cards for ~ccusim simulations. Two inverter circuits, one in CMOS and one in BiCMOS were designed to drive a 5OpF load. The BiCMOS circuit was determined to be four times faster, less temperature dependent, and considerably smaller than its CMOS counterpart. These results lead to a final conclusion favoring the development and use of BiCMOS here at RIT.
Bipolar Device Fabrication Using Rit's Cmos Technology To Develop A Bicmos Process, Luigi Ternullo Jr
Bipolar Device Fabrication Using Rit's Cmos Technology To Develop A Bicmos Process, Luigi Ternullo Jr
Journal of the Microelectronic Engineering Conference
An NPN bipolar transistor process was designed and fabricated for incorporation with RIT’s N well CMOS technology to develop BiCMOS devices. The only additions to the CMOS process were the base masking step, base implant, and drive. Base dose was varied to achieve current gains of 50, 100, and 200 using SUPREM-3. Unfortunately, do to an incomplete etch of the collector region, a rework had to be performed, whose added temperature steps pushed the emitter through the base.
Ferroelectric Thin Film Research At Rit, John P. Verostek
Ferroelectric Thin Film Research At Rit, John P. Verostek
Journal of the Microelectronic Engineering Conference
At RIT, a sol-gel method is being used to synthesize lead zirconate titanate (PZT). Techniques available to characterize these films include scanning electron microscopy ellipsometry, energy dispersive analysis using X-rays (EDAX), and X-ray diffraction (XRD) to determine crystallinity. After heating above the Curie temperature, XRD indicated that a perovskite structure, known to be ferroelectric, was obtained for a PZT film.
Design And Fabrication Of A Lateral Bipolar Pnp Transistor Compatible With Rit's Double Diffused Process, James A. Will Ii
Design And Fabrication Of A Lateral Bipolar Pnp Transistor Compatible With Rit's Double Diffused Process, James A. Will Ii
Journal of the Microelectronic Engineering Conference
A chip was designed containing lateral bipolar PNP devices with base widths ranging from four to ten microns. Vertical NPN devices were included in the designs. The transistors were fabricated using a double diffused process employing solid sources. Two different boron collector/emitter predepositions were performed in order to study the effects of the p-type diffusion sheet resistance on both lateral PNP and vertical NPN devices. Testing of the lateral PNP devices shows very small Early voltages for the five and six micron designs, while the four micron design exhibits punchthrough.
Spin On Glass Etch Processing For The Rit Nmos Process, William Roberts
Spin On Glass Etch Processing For The Rit Nmos Process, William Roberts
Journal of the Microelectronic Engineering Conference
ACCUGLASS 104 was characterized for four micron via etching. The quality of the Spin On Glass (SOG) layer was improved by increasing the cure temperature to 600 degrees c for one hour. A buffered hydrofloric acid diluted 100:1 produced an etch rate of 2700 Angstroms per minute. A plasma etching process was design with a gas mixture of CHF3/CF4/02 in a ratio of 10:3:1.5 wit a regal 700 plasma etcher. The SOG etch rate of this mixture was 600 Angstroms per minute. The selectivity of this plasma for SOG to poly silicon was 12:1. The wet process produced better image …
Standard Cell Realization For The Mentor Graphics Cad Environment, Bion Pohl
Standard Cell Realization For The Mentor Graphics Cad Environment, Bion Pohl
Journal of the Microelectronic Engineering Conference
A common way of designing microelectronic circuits is by the use of standard cells. In advance systems the circuit can be read from a schematic diagram and the computer will select and place the cells and layout the signal paths automatically. In order to do so the computer needs a representation of these cells and a description of the routing design rules. The format and content of these descriptions were investigated for the Mentor Graphics IDEA system and a procedure for building libraries of standard cells was developed. The related data files were then developed to allow the creation of …
Design And Fabrication Of A Pn Junction Photodiode Array, Richard Rogoff
Design And Fabrication Of A Pn Junction Photodiode Array, Richard Rogoff
Journal of the Microelectronic Engineering Conference
An array of photodiodes consisting of various areas and/or metallization schemes were fabricated for use in a photodiode array. The two gate metals used were Aluminum and Aluminum/Ytterbium. The standard RIT PMOS process was modified to obtain a shallow junction depth for the photodiode. All the diodes generated a photocurrent when illuminated, but the Aluminum metal scheme produced better results due to higher open circuit voltages and short circuit currents. The fill factor was also much better on these diodes.
Multi-Point Cleanroom Monitoring, Andrew La Pietra
Multi-Point Cleanroom Monitoring, Andrew La Pietra
Journal of the Microelectronic Engineering Conference
The feasibility of installing a multi-point particle monitoring system in the Rochester Institute of Technology Class 1000 Cleanroom at work level was examined. This consisted of monitoring 10 separate locations in the cleanroom at work level, including flow hoods, processing equipment and room air. An RS1 procedure was written to generate control charts and count information. The results showed that during low and high activity at a station the particle counts were in and out of process limits, respectively. Recommendations were made concerning installation of a complete system.
Plasma Etch Optimization Of Silicon Dioxide With A Resist Mask, Eric P. Meister
Plasma Etch Optimization Of Silicon Dioxide With A Resist Mask, Eric P. Meister
Journal of the Microelectronic Engineering Conference
A dry etch process was developed and characterized to etch silicon dioxide (Si02). Characterization included increasing the etch rate o-f Si02 while decreasing the etch rate of a KTIB2O positive photoresist mask, which is used in RIT’s fabrication processes. Successful masking and etching of silicon dioxide occurred with 15 sccm CHF3 mixed with 6 sccm 02 at a chamber pressure of 750 - 800 mtorr and a power of 100 watts.
Characterization Of Integrated Injection Logic, Tu T. Phan
Characterization Of Integrated Injection Logic, Tu T. Phan
Journal of the Microelectronic Engineering Conference
Integrated Injection Logic gates (IlL) were fabricated at RIT by the use of a double diffused, four mask process. The IlL devices contained neither a buried contact nor an epitaxial layer. The propagation delay time of invertor gates was measured at different injection current levels.
Contamination In Rit Processing, Daniel C. Shire
Contamination In Rit Processing, Daniel C. Shire
Journal of the Microelectronic Engineering Conference
Contamination during processing in RIT’S cleanroom facility is a leading cause in the failure of fabricated devices and circuits. Detection of these contaminants is possible using an ESTEK WIS-600 surface inspection system. Before and after particle counts were taken using this system when processing wafers in many common RIT procedures. It was found that contamination levels were significant in most areas, and cleaning procedures were useful only to remove large particles.
Design Of Test Die For Monitoring Manufacturing At Rit, Craig R. Klem
Design Of Test Die For Monitoring Manufacturing At Rit, Craig R. Klem
Journal of the Microelectronic Engineering Conference
This project developed a test chip designed to standardize the testing requirements and characterize bipolar, PMOS and CMOS processes at Rochester Institute of Technology. The comon process monitors were designed to test resistivity, opens and shorts, contact resistance and capacitance. The photolithograPhic monitors were designed to test image resolution and alignment. Process specific discrete devices were designed to test parainetrics and leakage currents. The test chip dies were primarily designed to be inserted onto the mask to eliminate the the need for process monitors on each die and secondly, to periodically monitor the performance of a student run integrated circuit …
University Clean Room Management Program, William P. Acito Jr
University Clean Room Management Program, William P. Acito Jr
Journal of the Microelectronic Engineering Conference
Implementation of a computerized clean room monitoring system at the RIT facility and the benefits of the RIT Management Program are discussed in this paper. Clean room parameters of interest with respect to environment, contamination, and process control were identified and the management of a commercial and university clean room will be contrasted.