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Rit Process And Device Simulation With Microtec, Charles R. Overbeck
Rit Process And Device Simulation With Microtec, Charles R. Overbeck
Journal of the Microelectronic Engineering Conference
Microtec, a diffusion-drift model simulator by Siborg Systems, Inc., was used to simulate RIT’s process for a 2-micron NFET (Long Channel), a scaled down NFET (Short Channel), and our new advanced CMOS Process NFET. The accuracy of the simulator was tested with voltage threshold curves, sub-threshold characteristic tests, potential distribution plots, doping profiles, and oxide growth measurements. Microtec proved to be able to easily model RIT’s device performance and process characteristics with only a small amount of modification.
Copper Interconnect Development At Rit, Ashish Kushwaha
Copper Interconnect Development At Rit, Ashish Kushwaha
Journal of the Microelectronic Engineering Conference
Aluminum is the current metal of choice for metallization in the IC industry. However, serious electromigration problems, and inferior thermal stability limit its performance and reliability. Copper is an attractive alternative having higher electrical conductivity and improved electromigration performance compared to Aluminum. However, Cu is a fast diffuser in Si, Si02, and interlevel dielectrics (ILD). To eliminate this issue, a layer of diffusion barrier (DB) material which is conducting, chemically passive with Copper, has good adhesion properties with Cu and ltD and has high thermal stability is required. Damascene process for Cu was utilized to pattern the wafers in this …
Development Of Lto Lpcvd Process For 6" Wafers At Rit, Karthika Sivagurunathan
Development Of Lto Lpcvd Process For 6" Wafers At Rit, Karthika Sivagurunathan
Journal of the Microelectronic Engineering Conference
Low Temperature Oxide (LTO) thin films were prepared using a Low Pressure Chemical Vapor Deposition process. By employing statistically designed experiments, the number of experimental runs required was minimized. The full-factorial experimental design was set up to examine effects temperature, gas flow and pressure had on deposition rate, wafer to wafer uniformity, within the wafer uniformity and within run uniformity. The average deposition rate found to be 112A per minute. The LTO baseline process conditions optimized based on the results of this project are: Temperature of 410C, pressure of 33OmTorr and gas flow ratio of 0.55.