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Full-Text Articles in VLSI and Circuits, Embedded and Hardware Systems

Evaluation And Analysis Of Null Convention Logic Circuits, John Davis Brady Dec 2019

Evaluation And Analysis Of Null Convention Logic Circuits, John Davis Brady

Graduate Theses and Dissertations

Integrated circuit (IC) designers face many challenges in utilizing state-of-the-art technology nodes, such as the increased effects of process variation on timing analysis and heterogeneous multi-die architectures that span across multiple technologies while simultaneously increasing performance and decreasing power consumption. These challenges provide opportunity for utilization of asynchronous design paradigms due to their inherent flexibility and robustness.

While NULL Convention Logic (NCL) has been implemented in a variety of applications, current literature does not fully encompass the intricacies of NCL power performance across a variety of applications, technology nodes, circuit scale, and voltage scaling, thereby preventing further adoption and utilization …


Switching Trajectory Control For High Voltage Silicon Carbide Power Devices With Novel Active Gate Drivers, Shuang Zhao Aug 2019

Switching Trajectory Control For High Voltage Silicon Carbide Power Devices With Novel Active Gate Drivers, Shuang Zhao

Graduate Theses and Dissertations

The penetration of silicon carbide (SiC) semiconductor devices is increasing in the power industry due to their lower parasitics, higher blocking voltage, and higher thermal conductivity over their silicon (Si) counterparts. Applications of high voltage SiC power devices, generally 10 kV or higher, can significantly reduce the amount of the cascaded levels of converters in the distributed system, simplify the system by reducing the number of the semiconductor devices, and increase the system reliability.

However, the gate drivers for high voltage SiC devices are not available on the market. Also, the characteristics of the third generation 10 kV SiC MOSFETs …


Hardware Ip Classification Through Weighted Characteristics, Brendan Mcgeehan May 2019

Hardware Ip Classification Through Weighted Characteristics, Brendan Mcgeehan

Graduate Theses and Dissertations

Today’s business model for hardware designs frequently incorporates third-party Intellectual Property (IP) due to the many benefits it can bring to a company. For instance, outsourcing certain components of an overall design can reduce time-to-market by allowing each party to specialize and perfect a specific part of the overall design. However, allowing third-party involvement also increases the possibility of malicious attacks, such as hardware Trojan insertion. Trojan insertion is a particularly dangerous security threat because testing the functionality of an IP can often leave the Trojan undetected. Therefore, this thesis work provides an improvement on a Trojan detection method known …


Asynchronous Circuit Synthesis Using Multi-Threshold Null Convention Logic, Nicholas Renoudet Mize May 2019

Asynchronous Circuit Synthesis Using Multi-Threshold Null Convention Logic, Nicholas Renoudet Mize

Graduate Theses and Dissertations

As the demand for an energy-efficient alternative to traditional synchronous circuit design grows, hardware designers must reconsider the traditional clock tree. By doing away with the constrains of a clock, asynchronous sequential circuit designs can achieve a much greater level of efficiency. The utilization of asynchronous logic synthesis flows has enabled researchers to better implement asynchronous circuit designs which have been optimized using the same industry standard tools that are already used in sequential synchronous designs. This thesis offers a new flow for such tools which implements the MTNCL asynchronous circuit architecture.


Model Development And Assessment Of The Gate Network In A High-Performance Sic Power Module, William Austin Curbow May 2019

Model Development And Assessment Of The Gate Network In A High-Performance Sic Power Module, William Austin Curbow

Graduate Theses and Dissertations

The main objective of this effort is to determine points of weakness in the gate network of a high-performance SiC power module and to offer remedies to these issues to increase the overall performance, robustness, and reliability of the technology. In order to accomplish this goal, a highly accurate model of the gate network is developed through three methods of parameter extraction: calculation, simulation, and measurement. A SPICE model of the gate network is developed to analyze four electrical issues in a high-speed, SiC-based power module including the necessary internal gate resistance for damping under-voltage and over-voltage transients, the disparity …