VLSI and Circuits, Embedded and Hardware Systems Commons^™

Hot Wire Anemoteter, Michael S. Potash, Albert D. Helfrick

Publications

A hot wire anemometer circuit has a calibrate subcircuit and an operate subcircuit which are selectively invoked via a user-activate mode switch. The calibrate subcircuit includes a detector configured to compare an amplified sensor voltage with an amplified drive voltage and output an indicator signal when the two voltages match. The drive voltage is derived from a user-adjusted drive resistance of a bridge subcircuit. The operate circuit includes a feedback loop which provides a signal to a bride node of a bridge circuit. After a sensor is connected to the anemometer circuit, the drive resistance is adjusted until the indicator …

An Rs-485 Transceiver In A Silicon Carbide Cmos Process, Maria Raquel Benavides Herrera

Graduate Theses and Dissertations

This thesis presents the design, simulation and test results of a silicon carbide (SiC) RS-485 transceiver for high temperature applications. This circuit is a building block in the design and fabrication of a digital data processing and control system. Automation processes for extreme environments, remote connection to high temperature locations, deep earth drilling, and high temperature data acquisition are some of the potential applications for such a system. The transceiver was designed and developed in a 1.2 µm SiC-CMOS process by Raytheon Systems, Ltd. (UK). It has been tested with a supply voltage of 12 V and 15 V, temperatures …

Asic Design To Support Low Power High Voltage Power Supply For Radiation Monitoring Applications, Daniel Rogge

Department of Electrical and Computer Engineering: Dissertations, Theses, and Student Research

A low power high voltage power supply is designed for use in a long duration radiation monitoring system. The supply employs a flexible pulse frequency modulation switching controller implemented in a 0.35 $\mu$m CMOS technology. The controller drives and regulates a flyback transformer driven 12-stage Cockroft-Walton voltage multiplier chain. The chain provides bias for the dynodes of a photomultiplier tube. The supply voltage is selectable via a 12-bit on-chip digital to analog converter. The system is designed for low power operation and immunity to supply voltage variation as the application is battery-powered.

Advisors: Sina Balkir and Michael Hoffman

Cmos Compatible Memristor Networks For Brain-Inspired Computing, Can Li

Doctoral Dissertations

In the past decades, the computing capability has shown an exponential growth trend, which is observed as Moore’s law. However, this growth speed is slowing down in recent years mostly because the down-scaled size of transistors is approaching their physical limit. On the other hand, recent advances in software, especially in big data analysis and artificial intelligence, call for a break-through in computing hardware. The memristor, or the resistive switching device, is believed to be a potential building block of the future generation of integrated circuits. The underlying mechanism of this device is different from that of complementary metal-oxide-semiconductor (CMOS) …

Multivariate Analysis For The Quantification Of Transdermal Volatile Organic Compounds In Humans By Proton Exchange Membrane Fuel Cell System, Ahmed Hasnain Jalal

FIU Electronic Theses and Dissertations

In this research, a proton exchange membrane fuel cell (PEMFC) sensor was investigated for specific detection of volatile organic compounds (VOCs) for point-of-care (POC) diagnosis of the physiological conditions of humans. A PEMFC is an electrochemical transducer that converts chemical energy into electrical energy. A Redox reaction takes place at its electrodes whereas the volatile biomolecules (e.g. ethanol) are oxidized at the anode and ambient oxygen is reduced at the cathode. The compounds which were the focus of this investigation were ethanol (C₂H₅OH) and isoflurane (C₃H₂ClF₅O), but theoretically, the sensor …

On-Chip Communication And Security In Fpgas, Shivukumar Basanagouda Patil

Masters Theses

Innovations in Field Programmable Gate Array (FPGA) manufacturing processes and architectural design have led to the development of extremely large FPGAs. There has also been a widespread adaptation of these large FPGAs in cloud infrastructures and data centers to accelerate search and machine learning applications. Two important topics related to FPGAs are addressed in this work: on-chip communication and security. On-chip communication is quickly becoming a bottleneck in to- day’s large multi-million gate FPGAs. Hard Networks-on-Chip (NoC), made of fixed silicon, have been shown to provide low power, high speed, flexible on-chip communication. An iterative algorithm for routing pre-scheduled time-division-multiplexed …

Investigating The Effect Of Detecting And Mitigating A Ring Oscillator-Based Hardware Trojan, Lakshmi Ramakrishnan

Electrical Engineering Theses and Dissertations

The outsourcing of the manufacturing process of integrated circuits to fabrications plants all over the world has exposed these chips to several security threats, especially at the hardware level. There have been instances of malicious circuitry, such as backdoors, being added to circuits without the knowledge of the chip designers or vendors. Such threats could be immensely powerful and dangerous against confidentiality, among other vulnerabilities.

Defense mechanisms against such attacks have been probed and defense techniques have been developed. But with the passage of time, attack techniques have improved immensely as well. From directly observing the inputs or outputs, adversaries …

Techniques Of Energy-Efficient Vlsi Chip Design For High-Performance Computing, Zhou Zhao

LSU Doctoral Dissertations

How to implement quality computing with the limited power budget is the key factor to move very large scale integration (VLSI) chip design forward. This work introduces various techniques of low power VLSI design used for state of art computing. From the viewpoint of power supply, conventional in-chip voltage regulators based on analog blocks bring the large overhead of both power and area to computational chips. Motivated by this, a digital based switchable pin method to dynamically regulate power at low circuit cost has been proposed to make computing to be executed with a stable voltage supply. For one of …

Efficacy Of Multi-Threshold Null Convention Logic In Low-Power Applications, Brent Bell

Graduate Theses and Dissertations

In order for an asynchronous design paradigm such as Multi-Threshold NULL Convention Logic (MTNCL) to be adopted by industry, it is important for circuit designers to be aware of its advantages and drawbacks especially with respect to power usage. The power tradeoff between MTNCL and synchronous designs depends on many different factors including design type, circuit size, process node, and pipeline granularity. Each of these design dimensions influences the active power and the leakage power comparisons. This dissertation analyzes the effects of different design dimensions on power consumption and the associated rational for these effects. Results show that while MTNCL …

Asic Design Of Rf Energy Harvester Using 0.13um Cmos Technology, Jainish K. Zaveri

Master's Theses

Recent advances in wireless sensor nodes, data acquisition devices, wearable and implantable medical devices have paved way for low power (sub 50uW) devices. These devices generally use small solid state or thin film batteries for power supply which need replacement or need to be removed for charging. RF energy harvesting technology can be used to charge these batteries without the need to remove the battery from the device, thus providing a sustainable power supply. In other cases, a battery can become unnecessary altogether. This enables us to deploy wireless network nodes in places where regular physical access to the nodes …

Cmos Radioactive Isotope Identification With Multichannel Analyzer And Embedded Neural Network, Samuel Murray

Department of Electrical and Computer Engineering: Dissertations, Theses, and Student Research

A radiation detection and identification system is designed and implemented to perform gamma ray spectroscopy on radioactive sources and identify which isotopes are present in the sources. A multichannel analyzer is implemented on an ASIC to process the signal produced from gamma rays detected by a scintillator and photomultiplier tube and to quantize the gamma ray energies to build a histogram. A fast, low memory embedded neural network is implemented on a microcontroller ASIC to identify the isotopes present in the gamma ray histogram produced by the multichannel analyzer in real time.

Advisors: Sina Balkir and Michael Hoffman

Skybridge-3d-Cmos: A Fine-Grained Vertical 3d-Cmos Technology Paving New Direction For 3d Ic, Jiajun Shi

Doctoral Dissertations

2D CMOS integrated circuit (IC) technology scaling faces severe challenges that result from device scaling limitations, interconnect bottleneck that dominates power and performance, etc. 3D ICs with die-die and layer-layer stacking using Through Silicon Vias (TSVs) and Monolithic Inter-layer Vias (MIVs) have been explored in recent years to generate circuits with considerable interconnect saving for continuing technology scaling. However, these 3D IC technologies still rely on conventional 2D CMOS’s device, circuit and interconnect mindset showing only incremental benefits while adding new challenges reliability issues, robustness of power delivery network design and short-channel effects as technology node scaling. Skybridge-3D-CMOS (S3DC) is …

Analog Signal Processing Solutions And Design Of Memristor-Cmos Analog Co-Processor For Acceleration Of High-Performance Computing Applications, Nihar Athreyas

Doctoral Dissertations

Emerging applications in the field of machine vision, deep learning and scientific simulation require high computational speed and are run on platforms that are size, weight and power constrained. With the transistor scaling coming to an end, existing digital hardware architectures will not be able to meet these ever-increasing demands. Analog computation with its rich set of primitives and inherent parallel architecture can be faster, more efficient and compact for some of these applications. The major contribution of this work is to show that analog processing can be a viable solution to this problem. This is demonstrated in the three …

Genetic Algorithm Amplifier Biasing System (Gaabs): Genetic Algorithm For Biasing On Differential Analog Amplifiers, Sean Whalen

Computer Engineering

Genetic Algorithm Amplifier Biasing System (GAABS) - Senior Project Analysis

Summary of Functional Requirements

This project integrates LTSpice with a python script that runs a genetic algorithm to bias a differential amplifier. The system biases the amplifier with 2 different voltages, the base voltage for the PNP BJTs of the active loads and a voltage controlling the current of the current sink. The project runs via a python script, gets data from LTSpice’s command line call, and iteratively runs until the system is biased to achieve the greatest gain on an arbitrary input voltage.

Primary Constraints

Some of the main …

Arm Mke1xf Mcu Replatform, Nathan Hong, Derek Lung, Japsimran Singh, Bevin Tang

Computer Engineering

After Cal Poly Racing’s electrical team began to hit the technical limits of the ADC and other I/O features of the current 8-bit Atmel AT90 microcontroller unit, it became clear that an upgrade was due. This replatforming project takes the functionalities of the old, 8-bit architecture, and aims to provide a 32-bit version using the ARM MKE1xF MCU. With the idea of having a working PCB as a stretch goal, the scope of the library development was limited to enable base functionality. Thus, the only libraries developed were for the Timer, ADC, SPI, UART, and CAN. Additionally, this document discusses …

Differential Power Analysis In-Practice For Hardware Implementations Of The Keccak Sponge Function, Nathaniel Graff

Master's Theses

The Keccak Sponge Function is the winner of the National Institute of Standards and Technology (NIST) competition to develop the Secure Hash Algorithm-3 Standard (SHA-3). Prior work has developed reference implementations of the algorithm and described the structures necessary to harden the algorithm against power analysis attacks which can weaken the cryptographic properties of the hash algorithm. This work demonstrates the architectural changes to the reference implementation necessary to achieve the theoretical side channel-resistant structures, compare their efficiency and performance characteristics after synthesis and place-and-route when implementing them on Field Programmable Gate Arrays (FPGAs), publish the resulting implementations under the …

Metrology Computer Redesign, Natalie Lizama, Melinda Ong, Mitchell Aiken

Electrical Engineering

We are M[EE]² and our project is to redesign Micro-Vu’s metrology computer (the Q16) with modern components and updated firmware. Metrology machines take high precision and high accuracy measurements, and a computer attached to each machine reads out the measurements. We will be redesigning the logic and display circuit boards on the Q16. The ports and communication methods with the machine will stay the same as it must be a drop-in replacement.

The motivation behind the redesign stems from the age of the current design. The current design was created in 1986, and has not had significant modifications since. …

Portable High-Definition Audio Spectrum Analyzer, Alex Zahn, Jamie Corr

Electrical Engineering

The Portable High-definition Audio Spectrum Analyzer (PHASA) allows the user to visualize the audio frequency spectrum of an incoming line-level stereo audio signal. Upon pressing the touch screen spectrum graph, the PHASA displays the corresponding frequency and volume levels as well as crosshairs at the touched location. The PHASA features multiple left/right channel display modes— Left channel only, right channel only, both channels simultaneously, and the average between the two channels. The PHASA features multiple resolution display modes (standard-resolution and high-resolution) and multiple dynamics display modes (standard dynamics, averaging, and peak/hold). The PHASA accepts input audio via a 1/4" TRS …

High-Speed Single-Channel Sar Adc Using Coarse And Fine Comparators With Background Comparator Offset Calibration, Guanhua Wang

Electrical Engineering Theses and Dissertations

A 1-GS/s 8-bit single-channel successive-approximation-register (SAR) analog-to-digital converter (ADC) using coarse and fine comparators with fully background comparator offset calibration is presented. Low-power coarse comparators and low-noise fine comparators are both employed to improve the comparator power efficiency. Non-binary digital-to-analog converter (DAC) with redundancy is employed to tolerate possible errors in the most-significant-bit (MSB) decisions. A novel comparator offset calibration scheme is proposed to remove the offsets between the different comparators, without slowing down the speed of the SAR conversion. The prototype ADC is simulated in a 28 nm CMOS technology and achieves an SNDR of 42.13 dB near Nyquist …

Low Latency Intrusion Detection In Smart Grids, Israel Zairi Akingeneye

Graduate Theses and Dissertations

The transformation of traditional power grids into smart grids has seen more new technologies such as communication networks and smart meters (sensors) being integrated into the physical infrastructure of the power grids. However, these technologies pose new vulnerabilities to the cybersecurity of power grids as malicious attacks can be launched by adversaries to attack the smart meters and modify the measurement data collected by these meters. If not timely detected and removed, these attacks may lead to inaccurate system state estimation, which is critical to the system operators for control decisions such as economic dispatch and other related functions.

This …

Detecting Suicide Risk From Wristworn Activity Tracker Data Using Machine Learning Approaches, Pallavi Atluri

Electrical Engineering Theses

Suicide is a prevalent cause of death worldwide and depression is a primary concern of many suicidal acts. It is possible that an individual during depression never has any suicidal thoughts at all. On the other hand, some individuals in stable condition with no apparent symptoms of depression feel urges to commit suicide (suicidal ideation). Many such individuals never let anyone know what they are feeling or planning. Suicidal ideation considered an important precursor to suicidal acts.

Detecting the suicide risk in individuals with mood disorders is a major challenge. The current clinical practice to assess suicide risk in these …

Applications Of Physical Unclonable Functions On Asics And Fpgas, Mohammad Usmani

Masters Theses

With the ever-increasing demand for security in embedded systems and wireless sensor networks, we require integrating security primitives for authentication in these devices. One such primitive is known as a Physically Unclonable Function. This entity can be used to provide security at a low cost, as the key or digital signature can be generated by dedicating a small part of the silicon die to these primitives which produces a fingerprint unique to each device. This fingerprint produced by a PUF is called its response. The response of PUFs depends upon the process variation that occurs during the manufacturing process. In …

General Design Procedure For Free And Open-Source Hardware For Scientific Equipment, Shane W. Oberloier, Joshua M. Pearce

Joshua M. Pearce

Distributed digital manufacturing of free and open-source scientific hardware (FOSH) used for scientific experiments has been shown to in general reduce the costs of scientific hardware by 90–99%. In part due to these cost savings, the manufacturing of scientific equipment is beginning to move away from a central paradigm of purchasing proprietary equipment to one in which scientists themselves download open-source designs, fabricate components with digital manufacturing technology, and then assemble the equipment themselves. This trend introduces a need for new formal design procedures that designers can follow when targeting this scientific audience. This study provides five steps in the …

Memory-Aware Scheduling For Fixed Priority Hard Real-Time Computing Systems, Gustavo A. Chaparro-Baquero

FIU Electronic Theses and Dissertations

As a major component of a computing system, memory has been a key performance and power consumption bottleneck in computer system design. While processor speeds have been kept rising dramatically, the overall computing performance improvement of the entire system is limited by how fast the memory can feed instructions/data to processing units (i.e. so-called memory wall problem). The increasing transistor density and surging access demands from a rapidly growing number of processing cores also significantly elevated the power consumption of the memory system. In addition, the interference of memory access from different applications and processing cores significantly degrade the …

Randomized Routing On Fat-Trees, Ronald I. Greenberg, Charles E. Leiserson

Ronald Greenberg

Fat-trees are a class of routing networks for hardware-efficient parallel computation. This paper presents a randomized algorithm for routing messages on a fat-tree. The quality of the algorithm is measured in terms of the load factor of a set of messages to be routed, which is a lower bound on the time required to deliver the messages. We show that if a set of messages has load factor lambda on a fat-tree with n processors, the number of delivery cycles (routing attempts) that the algorithm requires is O(lambda + lg n lg lg n) with probability 1-O(1/n). The best previous …

The Fat-Pyramid And Universal Parallel Computation Independent Of Wire Delay, Ronald I. Greenberg

Ronald Greenberg

This paper shows that a fat-pyramid of area Θ(A) requires only O(log A) slowdown to simulate any competing network of area A under very general conditions. The result holds regardless of the processor size (amount of attached memory) and number of processors in the competing networks as long as the limitation on total area is met. Furthermore, the result is valid regardless of the relationship between wire length and wire delay. We especially focus on elimination of the common simplifying assumption that unit time suffices to traverse a wire regardless of its length, since the assumption becomes more and more …

Randomized Routing On Fat-Trees, Ronald I. Greenberg

Ronald Greenberg

Fat-trees are a class of routing networks for hardware-efficient parallel computation. This paper presents a randomized algorithm for routing messages on a fat-tree. The quality of the algorithm is measured in terms of the load factor of a set of messages to be routed, which is a lower bound on the time required to deliver the messages. We show that if a set of messages has load factor lambda on a fat-tree with n processors, the number of delivery cycles (routing attempts) that the algorithm requires is O(lambda+lgnlglgn) with probability 1-O(1/ …

Universal Wormhole Routing, Ronald I. Greenberg, Hyeong-Cheol Oh

Ronald Greenberg

In this paper, we examine the wormhole routing problem in terms of the “congestion” c and “dilation” d for a set of packet paths. We show, with mild restrictions, that there is a simple randomized algorithm for routing any set of P packets in O(cdη+cLηlogP) time with high probability, where L is the number of flits in a packet, and η=min{d,L}; only a constant number of flits are stored in each queue at any time. Using this result, we show that a fat-tree network of area Θ(A) can simulate wormhole routing on any network of comparable area with O(log^3 A) …

Single-Layer Channel Routing And Placement With Single-Sided Nets, Ronald I. Greenberg, Jau-Der Shih

Ronald Greenberg

This paper considers the optimal offset, feasible offset, and optimal placement problems for a more general form of single-layer VLSI channel routing than has usually been considered in the past. Most prior works require that every net has exactly one terminal on each side of the channel. As long as only one side of the channel contains multiple terminals of the same net, we provide linear-time solutions to all three problems. Such results are implausible if the placement of terminals is entirely unrestricted; in fact, the size of the output for the feasible offset problem may be Ω(n^2). The linear-time …

On The Difficulty Of Manhattan Channel Routing, Ronald I. Greenberg, Joseph Jaja, Sridhar Krishnamurthy

Ronald Greenberg

We show that channel routing in the Manhattan model remains difficult even when all nets are single-sided. Given a set of n single-sided nets, we consider the problem of determining the minimum number of tracks required to obtain a dogleg-free routing. In addition to showing that the decision version of the problem isNP-complete, we show that there are problems requiring at least d+Omega(sqrt(n)) tracks, where d is the density. This existential lower bound does not follow from any of the known lower bounds in the literature.