Open Access. Powered by Scholars. Published by Universities.®
VLSI and Circuits, Embedded and Hardware Systems Commons™
Open Access. Powered by Scholars. Published by Universities.®
Articles 1 - 2 of 2
Full-Text Articles in VLSI and Circuits, Embedded and Hardware Systems
Evaluation And Analysis Of Null Convention Logic Circuits, John Davis Brady
Evaluation And Analysis Of Null Convention Logic Circuits, John Davis Brady
Graduate Theses and Dissertations
Integrated circuit (IC) designers face many challenges in utilizing state-of-the-art technology nodes, such as the increased effects of process variation on timing analysis and heterogeneous multi-die architectures that span across multiple technologies while simultaneously increasing performance and decreasing power consumption. These challenges provide opportunity for utilization of asynchronous design paradigms due to their inherent flexibility and robustness.
While NULL Convention Logic (NCL) has been implemented in a variety of applications, current literature does not fully encompass the intricacies of NCL power performance across a variety of applications, technology nodes, circuit scale, and voltage scaling, thereby preventing further adoption and utilization …
Technology Mapping, Design For Testability, And Circuit Optimizations For Null Convention Logic Based Architectures, Farhad Alibeygi Parsan
Technology Mapping, Design For Testability, And Circuit Optimizations For Null Convention Logic Based Architectures, Farhad Alibeygi Parsan
Graduate Theses and Dissertations
Delay-insensitive asynchronous circuits have been the target of a renewed research effort because of the advantages they offer over traditional synchronous circuits. Minimal timing analysis, inherent robustness against power-supply, temperature, and process variations, reduced energy consumption, less noise and EMI emission, and easy design reuse are some of the benefits of these circuits. NULL Convention Logic (NCL) is one of the mainstream asynchronous logic design paradigms that has been shown to be a promising method for designing delay-insensitive asynchronous circuits.
This dissertation investigates new areas in NCL design and test and is made of three sections. The first section discusses …