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Full-Text Articles in VLSI and Circuits, Embedded and Hardware Systems

Asynchronous Mips Processors: Educational Simulations, Robert L. Webb Aug 2010

Asynchronous Mips Processors: Educational Simulations, Robert L. Webb

Master's Theses

The system clock has been omnipresent in most mainstream chip designs. While simplifying many design problems the clock has caused the problems of clock skew, high power consumption, electromagnetic interference, and worst-case performance. In recent years, as the timing constraints of synchronous designs have been squeezed ever tighter, the efficiencies of asynchronous designs have become more attractive. By removing the clock, these issues can be mitigated. How- ever, asynchronous designs are generally more complex and difficult to debug. In this paper I discuss the advantages of asynchronous processors and the specifics of some asynchronous designs, outline the roadblocks to asynchronous …


Multithreaded Computer Architecture: A Summary Of The State Of The Art, Robert Iannucci, Guang Gao, Robert Halstead, Burton Smith Dec 1993

Multithreaded Computer Architecture: A Summary Of The State Of The Art, Robert Iannucci, Guang Gao, Robert Halstead, Burton Smith

Robert A Iannucci

No abstract provided.


Parallel Machines: Parallel Machine Languages, Robert Iannucci Dec 1989

Parallel Machines: Parallel Machine Languages, Robert Iannucci

Robert A Iannucci

No abstract provided.