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VLSI and Circuits, Embedded and Hardware Systems Commons™

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Digital Circuits

2015

Articles 1 - 6 of 6

Full-Text Articles in VLSI and Circuits, Embedded and Hardware Systems

Data And Network Optimization Effect On Web Performance, Steven Rosenberg, Surbhi Dangi, Isuru Warnakulasooriya Dec 2015

Data And Network Optimization Effect On Web Performance, Steven Rosenberg, Surbhi Dangi, Isuru Warnakulasooriya

Surbhi Dangi

In this study, we measure the effects of two software approaches to improving data and network performance: 1. Content optimization and compression; and 2. Optimizing network protocols. We achieve content optimization and compression by means of BoostEdge by ActivNetworks and employ the SPDY network protocol by Google to lower the round trip time for HTTP transactions. Since the data and transport layers are separate, we conclude our investigation by studying the combined effect of these two techniques on web performance. Using document mean load time as the measure, we found that with and without packet loss, both BoostEdge and SPDY …

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Arithmetic Logic Unit Architectures With Dynamically Defined Precision, Getao Liang Dec 2015

Arithmetic Logic Unit Architectures With Dynamically Defined Precision, Getao Liang

Doctoral Dissertations

Modern central processing units (CPUs) employ arithmetic logic units (ALUs) that support statically defined precisions, often adhering to industry standards. Although CPU manufacturers highly optimize their ALUs, industry standard precisions embody accuracy and performance compromises for general purpose deployment. Hence, optimizing ALU precision holds great potential for improving speed and energy efficiency. Previous research on multiple precision ALUs focused on predefined, static precisions. Little previous work addressed ALU architectures with customized, dynamically defined precision. This dissertation presents approaches for developing dynamic precision ALU architectures for both fixed-point and floating-point to enable better performance, energy efficiency, and numeric accuracy. These new …

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Skybridge: A New Nanoscale 3-D Computing Framework For Future Integrated Circuits, Mostafizur Rahman Nov 2015

Skybridge: A New Nanoscale 3-D Computing Framework For Future Integrated Circuits, Mostafizur Rahman

Doctoral Dissertations

Continuous scaling of CMOS has been the major catalyst in miniaturization of integrated circuits (ICs) and crucial for global socio-economic progress. However, continuing the traditional way of scaling to sub-20nm technologies is proving to be very difficult as MOSFETs are reaching their fundamental performance limits [1] and interconnection bottleneck is dominating IC operational power and performance [2]. Migrating to 3-D, as a way to advance scaling, has been elusive due to inherent customization and manufacturing requirements in CMOS architecture that are incompatible with 3-D organization. Partial attempts with die-die [3] and layer-layer [4] stacking have their own limitations [5]. We …

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Threat Analysis, Countermeaures And Design Strategies For Secure Computation In Nanometer Cmos Regime, Raghavan Kumar Nov 2015

Threat Analysis, Countermeaures And Design Strategies For Secure Computation In Nanometer Cmos Regime, Raghavan Kumar

Doctoral Dissertations

Advancements in CMOS technologies have led to an era of Internet Of Things (IOT), where the devices have the ability to communicate with each other apart from their computational power. As more and more sensitive data is processed by embedded devices, the trend towards lightweight and efficient cryptographic primitives has gained significant momentum. Achieving a perfect security in silicon is extremely difficult, as the traditional cryptographic implementations are vulnerable to various active and passive attacks. There is also a threat in the form of "hardware Trojans" inserted into the supply chain by the untrusted third-party manufacturers for economic incentives. Apart …

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Function Verification Of Combinational Arithmetic Circuits, Duo Liu Jul 2015

Function Verification Of Combinational Arithmetic Circuits, Duo Liu

Masters Theses

Hardware design verification is the most challenging part in overall hardware design process. It is because design size and complexity are growing very fast while the requirement for performance is ever higher. Conventional simulation-based verification method cannot keep up with the rapid increase in the design size, since it is impossible to exhaustively test all input vectors of a complex design. An important part of hardware verification is combinational arithmetic circuit verification. It draws a lot of attention because flattening the design into bit-level, known as the bit-blasting problem, hinders the efficiency of many current formal techniques. The goal of …

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Managing And Leveraging Variations And Noise In Nanometer Cmos, Vikram B. Suresh Mar 2015

Managing And Leveraging Variations And Noise In Nanometer Cmos, Vikram B. Suresh

Doctoral Dissertations

Advanced CMOS technologies have enabled high density designs at the cost of complex fabrication process. Variation in oxide thickness and Random Dopant Fluctuation (RDF) lead to variation in transistor threshold voltage Vth. Current photo-lithography process used for printing decreasing critical dimensions result in variation in transistor channel length and width. A related challenge in nanometer CMOS is that of on-chip random noise. With decreasing threshold voltage and operating voltage; and increasing operating temperature, CMOS devices are more sensitive to random on-chip noise in advanced technologies. In this thesis, we explore novel circuit techniques to manage the impact of …

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