Open Access. Powered by Scholars. Published by Universities.®
VLSI and Circuits, Embedded and Hardware Systems Commons™
Open Access. Powered by Scholars. Published by Universities.®
- Institution
- Keyword
-
- 5G (1)
- 6G (1)
- AMBA Advanced High-Performance Bus (AHB) and Advanced eXensible Interface (AXI) (1)
- Advanced Encryption Standard (AES) (1)
- Analog Beamforming (1)
-
- Analog circuit design (1)
- Analog to digital converter (1)
- Antenna arrays (1)
- Application specific customization (1)
- Automatic synthesis (1)
- Chip design (1)
- Design Automation (1)
- Digital Beamforming (1)
- Digital circuit design (1)
- Electrical engineering (1)
- Electronic skin (1)
- FPGA (1)
- Genetic algorithm (1)
- High Performance Bus Architecture (1)
- High Security (1)
- Integrated circuits (1)
- Internet-of-Things (IoT) (1)
- Low Power (1)
- MIMO (1)
- Massive MIMO (1)
- Multi core (1)
- Multibeams (1)
- Multidimensional signal processing (1)
- Partitioning (1)
- Performance Evaluation Methodology (1)
Articles 1 - 6 of 6
Full-Text Articles in VLSI and Circuits, Embedded and Hardware Systems
Low-Power, Event-Driven System On A Chip For Charge Pulse Processing Applications, Joseph A. Schmitz
Low-Power, Event-Driven System On A Chip For Charge Pulse Processing Applications, Joseph A. Schmitz
Department of Electrical and Computer Engineering: Dissertations, Theses, and Student Research
This dissertation presents an electronic architecture and methodology capable of processing charge pulses generated by a range of sensors, including radiation detectors and tactile synthetic skin. These sensors output a charge signal proportional to the input stimulus, which is processed electronically in both the analog and digital domains. The presented work implements this functionality using an event-driven methodology, which greatly reduces power consumption compared to standard implementations. This enables new application areas that require a long operating time or compact physical dimensions, which would not otherwise be possible. The architecture is designed, fabricated, and tested in the aforementioned applications to …
Digital And Mixed Domain Hardware Reduction Algorithms And Implementations For Massive Mimo, Najath A. Mohomed
Digital And Mixed Domain Hardware Reduction Algorithms And Implementations For Massive Mimo, Najath A. Mohomed
FIU Electronic Theses and Dissertations
Emerging 5G and 6G based wireless communications systems largely rely on multiple-input-multiple-output (MIMO) systems to reduce inherently extensive path losses, facilitate high data rates, and high spatial diversity. Massive MIMO systems used in mmWave and sub-THz applications consists of hundreds perhaps thousands of antenna elements at base stations. Digital beamforming techniques provide the highest flexibility and better degrees of freedom for phased antenna arrays as compared to its analog and hybrid alternatives but has the highest hardware complexity.
Conventional digital beamformers at the receiver require a dedicated analog to digital converter (ADC) for every antenna element, leading to ADCs for …
Algorithms And Circuits For Analog-Digital Hybrid Multibeam Arrays, Paboda Viduneth A. Beruwawela Pathiranage
Algorithms And Circuits For Analog-Digital Hybrid Multibeam Arrays, Paboda Viduneth A. Beruwawela Pathiranage
FIU Electronic Theses and Dissertations
Fifth generation (5G) and beyond wireless communication systems will rely heavily on larger antenna arrays combined with beamforming to mitigate the high free-space path-loss that prevails in millimeter-wave (mmW) and above frequencies. Sharp beams that can support wide bandwidths are desired both at the transmitter and the receiver to leverage the glut of bandwidth available at these frequency bands. Further, multiple simultaneous sharp beams are imperative for such systems to exploit mmW/sub-THz wireless channels using multiple reflected paths simultaneously. Therefore, multibeam antenna arrays that can support wider bandwidths are a key enabler for 5G and beyond systems.
In general, N- …
A High Performance Advanced Encryption Standard (Aes) Encrypted On-Chip Bus Architecture For Internet-Of-Things (Iot) System-On-Chips (Soc), Xiaokun Yang
FIU Electronic Theses and Dissertations
With industry expectations of billions of Internet-connected things, commonly referred to as the IoT, we see a growing demand for high-performance on-chip bus architectures with the following attributes: small scale, low energy, high security, and highly configurable structures for integration, verification, and performance estimation.
Our research thus mainly focuses on addressing these key problems and finding the balance among all these requirements that often work against each other. First of all, we proposed a low-cost and low-power System-on-Chips (SoCs) architecture (IBUS) that can frame data transfers differently. The IBUS protocol provides two novel transfer modes – the block and state …
Application Specific Customization And Scalability Of Soft Multiprocessors, Deepak C. Unnikrishnan
Application Specific Customization And Scalability Of Soft Multiprocessors, Deepak C. Unnikrishnan
Masters Theses 1911 - February 2014
Soft multiprocessor systems exploit the plentiful computational resources available in field programmable devices. By virtue of their adaptability and ability to support coarse grained parallelism, they serve as excellent platforms for rapid prototyping and design space exploration of embedded multiprocessor applications. As complex applications emerge, careful mapping, processor and interconnect customization are critical to the overall performance of the multiprocessor system. In this thesis, we have developed an automated scalable framework to efficiently map applications written in a high-level programmer-friendly language to customizable soft-cores. The framework allows the user to specify the application in a high-level language called Streamit. After …
Genetic Algorithms Vs. Simulated Annealing: A Comparison Of Approaches For Solving The Circuit Partitioning Problem, Theodore W. Manikas, James T. Cain
Genetic Algorithms Vs. Simulated Annealing: A Comparison Of Approaches For Solving The Circuit Partitioning Problem, Theodore W. Manikas, James T. Cain
Computer Science and Engineering Research
An important stage in circuit design is placement, where components are assigned to physical locations on a chip. A popular contemporary approach for placement is the use of simulated annealing. While this approach has been shown to produce good placement solutions, recent work in genetic algorithms has produced promising results. The purpose of this study is to determine which approach will result in better placement solutions.
A simplified model of the placement problem, circuit partitioning, was tested on three circuits with both a genetic algorithm and a simulated annealing algorithm. When compared with simulated annealing, the genetic algorithm was found …