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Full-Text Articles in VLSI and Circuits, Embedded and Hardware Systems

Digital And Mixed Domain Hardware Reduction Algorithms And Implementations For Massive Mimo, Najath A. Mohomed Nov 2020

Digital And Mixed Domain Hardware Reduction Algorithms And Implementations For Massive Mimo, Najath A. Mohomed

FIU Electronic Theses and Dissertations

Emerging 5G and 6G based wireless communications systems largely rely on multiple-input-multiple-output (MIMO) systems to reduce inherently extensive path losses, facilitate high data rates, and high spatial diversity. Massive MIMO systems used in mmWave and sub-THz applications consists of hundreds perhaps thousands of antenna elements at base stations. Digital beamforming techniques provide the highest flexibility and better degrees of freedom for phased antenna arrays as compared to its analog and hybrid alternatives but has the highest hardware complexity.

Conventional digital beamformers at the receiver require a dedicated analog to digital converter (ADC) for every antenna element, leading to ADCs for …


Algorithms And Circuits For Analog-Digital Hybrid Multibeam Arrays, Paboda Viduneth A. Beruwawela Pathiranage Nov 2019

Algorithms And Circuits For Analog-Digital Hybrid Multibeam Arrays, Paboda Viduneth A. Beruwawela Pathiranage

FIU Electronic Theses and Dissertations

Fifth generation (5G) and beyond wireless communication systems will rely heavily on larger antenna arrays combined with beamforming to mitigate the high free-space path-loss that prevails in millimeter-wave (mmW) and above frequencies. Sharp beams that can support wide bandwidths are desired both at the transmitter and the receiver to leverage the glut of bandwidth available at these frequency bands. Further, multiple simultaneous sharp beams are imperative for such systems to exploit mmW/sub-THz wireless channels using multiple reflected paths simultaneously. Therefore, multibeam antenna arrays that can support wider bandwidths are a key enabler for 5G and beyond systems.

In general, N- …


A High Performance Advanced Encryption Standard (Aes) Encrypted On-Chip Bus Architecture For Internet-Of-Things (Iot) System-On-Chips (Soc), Xiaokun Yang Mar 2016

A High Performance Advanced Encryption Standard (Aes) Encrypted On-Chip Bus Architecture For Internet-Of-Things (Iot) System-On-Chips (Soc), Xiaokun Yang

FIU Electronic Theses and Dissertations

With industry expectations of billions of Internet-connected things, commonly referred to as the IoT, we see a growing demand for high-performance on-chip bus architectures with the following attributes: small scale, low energy, high security, and highly configurable structures for integration, verification, and performance estimation.

Our research thus mainly focuses on addressing these key problems and finding the balance among all these requirements that often work against each other. First of all, we proposed a low-cost and low-power System-on-Chips (SoCs) architecture (IBUS) that can frame data transfers differently. The IBUS protocol provides two novel transfer modes – the block and state …