VLSI and Circuits, Embedded and Hardware Systems Commons^™

Holistic Dram Enhancements: From Intrinsic In-Memory Operations To Robust Security Mechanisms, Ranyang Zhou

Dissertations

Dynamic Random-Access Memory (DRAM) is both the performance bottleneck and a critical security boundary of modern computing systems. Its physical properties make it an attractive substrate for near-data computation—yet those same properties expose it to disturbance-based hardware attacks. This dissertation argues that these two dimensions are not independent: the architectural choices that make DRAM efficient also reshape its threat landscape. Addressing both requires a unified approach to memory architecture and security co-design.

The first part of this dissertation attacks the memory wall through four processing-in-DRAM (PIM) frameworks. ReD-LUT and LT-PIM unify lookup-table arithmetic with charge-sharing logic, achieving up to 37.8x …

Demystifying Hardware Formal Verification For Undergraduate Education: A Risc-V Processor Case Study With Coursework Implementation, Riley A. Peters

Master's Theses

Hardware verification engineers apply formal methods to prove that a digital device always behaves according to its specification. This differs from traditional functional verification, in which engineers establish correctness by repeatedly sending test inputs to the device and comparing the outputs against a reference model. With the growing complexity of integrated circuits, the demand for digital verification engineers with formal methods experience has continued to increase. However, California Polytechnic State University: San Luis Obispo's current curriculum lacks dedicated material to prepare students for these roles.

This thesis seeks to address the lack of formal methods material through two efforts. First, …

Printer For Music Box, Chad Lewis, Caleb Murawski, Zion Smith, Bryan Tibbs

Williams Honors College, Honors Research Projects

The traditional method of creating music box sheet music involves manually punching holes into a paper strip using a hand-operated hole punch. This process involves precise knowledge of each note’s location and the ability to achieve perfect accuracy for hours.

The goal of this system is to automate this process, significantly reducing the time required while greatly improving the accuracy of the resulting music box playback. The user simply uploads a MIDI file of their choice into a user-friendly application. Here, the file is modified based on the user’s needs and sent to an automated hole-punching system to punch the …

Development Of Interactive Games On An Affordable Braille Display, Daniel Tsivkovski, Dylan Ravel, Maryam Etezad

Student Scholar Symposium Abstracts and Posters

Developing an affordable and STEM learning-focused Braille display addresses a significant disparity in the market for Braille displays, where most fail to provide a cost-effective, accessible, and education-oriented solution. This research aims to bridge this gap through innovative hardware and software development, offering a comprehensive learning experience to elementary school children (K-6) who are blind/visually impaired. The hardware features a piezo-electric tactile display that displays up to six Braille characters at once or a shape in an 8x8 pin array configuration. The educational software includes a user-friendly website packed with engaging STEM activities specifically designed for blind/visually impaired children. The …

Artificial Intelligence Applications For Grid-Connected Solar Inverters, Utkirjon Ubaydullaev, Sarvinoz Mirzaeva, Hasan Mustafoev

Chemical Technology, Control and Management

The increasing global demand for renewable energy has highlighted the importance of grid-connected solar inverters in ensuring efficient and stable power conversion. However, challenges such as fluctuations in solar energy generation, grid disturbances, and power quality issues necessitate advanced control strategies. The integration of artificial intelligence (AI) into solar inverters presents a transformative solution, enhancing performance, adaptability, and reliability in real-world applications.

This review explores the role of AI techniques, including machine learning (ML), deep learning (DL), fuzzy logic, and reinforcement learning (RL), in optimizing key inverter functionalities such as maximum power point tracking (MPPT), fault detection, power quality enhancement, …

Autonomous Landscape Exploration Rover Using Imaging Surface Navigation (Alexis), Noah Jones, Dominic Salupo

Williams Honors College, Honors Research Projects

The objective is to develop a small-form-factor rover prototype that can be used to prove out a novel traversal method for use on extraterrestrial surfaces. The novel traversal method being proposed is LIDAR/CV-enhanced navigation, provided by a detachable flight vehicle that can communicate with the rover. On planets with thin atmospheres, cold gas thrusters or similar may be needed, but for the scope of this project more traditional flight/propulsion methods will be used.

Resilient, Sustainable, And Secure Systems Support For Ultra-Low-Power Computational Things, Nicole Tobias

All Dissertations

Wireless battery-free and energy-harvesting devices are expanding the reach and vision of the Internet of Things, where trillions of embedded computational things interconnect ubiquitously around us and inform many different aspects of our everyday lives. Designing these systems without batteries and interconnecting wires lowers maintenance, environmental, and economic costs while also extending device lifetime and deployment opportunities. Over the last decade, research on these ultra-low-power embedded sensors and systems has dramatically increased — enabling new and exciting prospects in many different scientific fields, from smart building and health monitoring applications to animal and activity tracking.

These systems are not without …

Electronic Note-String Detector, Gavin Garcia-Rossi, Tommy Smail

Electrical Engineering

As the virtual space has become a dominant part of everyone’s day-to-day lives, many normal face-to-face interactions and services have not yet been facilitated by adapting technology. One of these prevailing areas is music lessons. Over Zoom meetings, or other virtual platforms, it is tremendously challenging to teach students. These challenges include recognizing student mistakes audibly and visually, and being able to give confident feedback on the incorrect notes played by learning musicians. Without having to delve into improving the complex systems that would be required to improve audio, video, and connection quality of these connections, we have another solution …

Qasm-To-Hls: A Framework For Accelerating Quantum Circuit Emulation On High-Performance Reconfigurable Computers, Anshul Maurya

Theses and Dissertations

High-performance reconfigurable computers (HPRCs) make use of Field-Programmable Gate Arrays (FPGAs) for efficient emulation of quantum algorithms. Generally, algorithm-specific architectures are implemented on the FPGAs and there is very little flexibility. Moreover, mapping a quantum algorithm onto its equivalent FPGA emulation architecture is challenging. In this work, we present an automation framework for converting quantum circuits to their equivalent FPGA emulation architectures. The framework processes quantum circuits represented in Quantum Assembly Language (QASM) and derives high-level descriptions of the hardware emulation architectures for High-Level Synthesis (HLS) on HPRCs. The framework generates the code for a heterogeneous architecture consisting of a …

Accelerating Machine Learning Inference For Satellite Component Feature Extraction Using Fpgas., Andrew Ekblad

Theses and Dissertations

Running computer vision algorithms requires complex devices with lots of computing power, these types of devices are not well suited for space deployment. The harsh radiation environment and limited power budgets have hindered the ability of running advanced computer vision algorithms in space. This problem makes running an on-orbit servicing detection algorithm very difficult. This work proposes using a low powered FPGA to accelerate the computer vision algorithms that enable satellite component feature extraction. This work uses AMD/Xilinx’s Zynq SoC and DPU IP to run model inference. Experiments in this work centered around improving model post processing by creating implementations …

Framework Of Hardware Trojan Detection Leveraging Structural Checking Tool, Rafael Dacanay Del Carmen

Graduate Theses and Dissertations

Since there is a significant demand for obtaining third-party soft Intellectual Property (IP) by first-party integrated circuit (IC) vendors, it is becoming easier for adversaries to insert malicious logic known as hardware Trojans into designs. Due to this, vendors need to find ways to screen the third-party IPs for possible security threats and then mitigate them. The development of the Structural Checking (SC) tool provides a solution to this issue. This tool analyzes the structure of an unknown soft IP design and creates a network of all the signals within the design and how they are connected to each other. …

Expanding Temperature Sensing For The Orion Bms 2, Samuel J. Parker

University Honors Theses

Formula SAE (FSAE) is an annual collegiate design competition that takes place across the globe. Portland State University’s team, Viking Motorsports, was committed to designing an Electric Vehicle (EV) for the 2021 FSAE competition. The team designed a completely custom lithium-ion cell battery that is managed by an Orion BMS 2 battery management system. The FSAE rulebook requires a robust temperature monitoring system for any EV power supply. The Orion BMS 2 can only directly collect data from eight temperature sensors, which is not enough to meet FSAE regulation. However, the BMS can be configured to monitor many more sensors …

Design Project: Smart Headband, John Michel, Jack Durkin, Noah Lewis

Williams Honors College, Honors Research Projects

Concussion in sports is a prevalent medical issue. It can be difficult for medical professionals to diagnose concussions. With the fast pace nature of many sports, and the damaging effects of concussions, it is important that any concussion risks are assessed immediately. There is a growing trend of wearable technology that collects data such as steps and provides the wearer with in-depth information regarding their performance. The Smart Headband project created a wearable that can record impact data and provide the wearer with a detailed analysis on their risk of sustaining a concussion. The Smart Headband uses accelerometers and gyroscopes …

Investigating Single Precision Floating General Matrix Multiply In Heterogeneous Hardware, Steven Harris

McKelvey School of Engineering Graduate Student Theses & Dissertations

The fundamental operation of matrix multiplication is ubiquitous across a myriad of disciplines. Yet, the identification of new optimizations for matrix multiplication remains relevant for emerging hardware architectures and heterogeneous systems. Frameworks such as OpenCL enable computation orchestration on existing systems, and its availability using the Intel High Level Synthesis compiler allows users to architect new designs for reconfigurable hardware using C/C++. Using the HARPv2 as a vehicle for exploration, we investigate the utility of several of the most notable matrix multiplication optimizations to better understand the performance portability of OpenCL and the implications for such optimizations on this and …

Side-Channel Power Resistance For Encryption Algorithms Using Implementation Diversity, Ivan M. Bow

Electrical and Computer Engineering ETDs

This thesis paper investigates countermeasures to hardware side-channel attacks and proposes a new solution to this ever growing threat against data integrity and security. The side-channel attack methods, differential power analysis and correlation power analysis, are both very powerful techniques and are used to gain access to secrets inside of a field programmable gate array that are otherwise inaccessible, in particular the cryptographic key for the Advanced Encryption Standard algorithm. To counter these attacks, we propose a method of changing the internal hardware configuration of the field programmable gate array using dynamic partial reconfiguration. Using this method, we change the …

Model Development And Assessment Of The Gate Network In A High-Performance Sic Power Module, William Austin Curbow

Graduate Theses and Dissertations

The main objective of this effort is to determine points of weakness in the gate network of a high-performance SiC power module and to offer remedies to these issues to increase the overall performance, robustness, and reliability of the technology. In order to accomplish this goal, a highly accurate model of the gate network is developed through three methods of parameter extraction: calculation, simulation, and measurement. A SPICE model of the gate network is developed to analyze four electrical issues in a high-speed, SiC-based power module including the necessary internal gate resistance for damping under-voltage and over-voltage transients, the disparity …

Hardware Ip Classification Through Weighted Characteristics, Brendan Mcgeehan

Graduate Theses and Dissertations

Today’s business model for hardware designs frequently incorporates third-party Intellectual Property (IP) due to the many benefits it can bring to a company. For instance, outsourcing certain components of an overall design can reduce time-to-market by allowing each party to specialize and perfect a specific part of the overall design. However, allowing third-party involvement also increases the possibility of malicious attacks, such as hardware Trojan insertion. Trojan insertion is a particularly dangerous security threat because testing the functionality of an IP can often leave the Trojan undetected. Therefore, this thesis work provides an improvement on a Trojan detection method known …

Low Latency Intrusion Detection In Smart Grids, Israel Zairi Akingeneye

Graduate Theses and Dissertations

The transformation of traditional power grids into smart grids has seen more new technologies such as communication networks and smart meters (sensors) being integrated into the physical infrastructure of the power grids. However, these technologies pose new vulnerabilities to the cybersecurity of power grids as malicious attacks can be launched by adversaries to attack the smart meters and modify the measurement data collected by these meters. If not timely detected and removed, these attacks may lead to inaccurate system state estimation, which is critical to the system operators for control decisions such as economic dispatch and other related functions.

This …

Asynchronous 3d (Async3d): Design Methodology And Analysis Of 3d Asynchronous Circuits, Francis Corpuz Sabado

Graduate Theses and Dissertations

This dissertation focuses on the application of 3D integrated circuit (IC) technology on asynchronous logic paradigms, mainly NULL Convention Logic (NCL) and Multi-Threshold NCL (MTNCL). It presents the Async3D tool flow and library for NCL and MTNCL 3D ICs. It also analyzes NCL and MTNCL circuits in 3D IC. Several FIR filter designs were implement in NCL, MTNCL, and synchronous architecture to compare synchronous and asynchronous circuits in 2D and 3D ICs. The designs were normalized based on performance and several metrics were measured for comparison. Area, interconnect length, power consumption, and power density were compared among NCL, MTNCL, and …

Hexarray: A Novel Self-Reconfigurable Hardware System, Fady Hussein

Boise State University Theses and Dissertations

Evolvable hardware (EHW) is a powerful autonomous system for adapting and finding solutions within a changing environment. EHW consists of two main components: a reconfigurable hardware core and an evolutionary algorithm. The majority of prior research focuses on improving either the reconfigurable hardware or the evolutionary algorithm in place, but not both. Thus, current implementations suffer from being application oriented and having slow reconfiguration times, low efficiencies, and less routing flexibility. In this work, a novel evolvable hardware platform is proposed that combines a novel reconfigurable hardware core and a novel evolutionary algorithm.

The proposed reconfigurable hardware core is a …

Design And Verification Environment For High-Performance Video-Based Embedded Systems, Michael Mefenza Nentedem

Graduate Theses and Dissertations

In this dissertation, a method and a tool to enable design and verification of computation demanding embedded vision-based systems is presented. Starting with an executable specification in OpenCV, we provide subsequent refinements and verification down to a system-on-chip prototype into an FPGA-Based smart camera. At each level of abstraction, properties of image processing applications are used along with structure composition to provide a generic architecture that can be automatically verified and mapped to the lower abstraction level. The result is a framework that encapsulates the computer vision library OpenCV at the highest level, integrates Accelera's System-C/TLM with UVM and QEMU-OS …

Enabling Runtime Self-Coordination Of Reconfigurable Embedded Smart Cameras In Distributed Networks, Franck Ulrich Yonga Yonga

Graduate Theses and Dissertations

Smart camera networks are real-time distributed embedded systems able to perform computer vision using multiple cameras. This new approach is a confluence of four major disciplines (computer vision, image sensors, embedded computing and sensor networks) and has been subject of intensive work in the past decades. The recent advances in computer vision and network communication, and the rapid growing in the field of high-performance computing, especially using reconfigurable devices, have enabled the design of more robust smart camera systems. Despite these advancements, the effectiveness of current networked vision systems (compared to their operating costs) is still disappointing; the main reason …

Idpal – A Partially-Adiabatic Energy-Efficient Logic Family: Theory And Applications To Secure Computing, Mihail T. Cutitaru

Electrical & Computer Engineering Theses & Dissertations

Low-power circuits and issues associated with them have gained a significant amount of attention in recent years due to the boom in portable electronic devices. Historically, low-power operation relied heavily on technology scaling and reduced operating voltage, however this trend has been slowing down recently due to the increased power density on chips. This dissertation introduces a new very-low power partially-adiabatic logic family called Input-Decoupled Partially-Adiabatic Logic (IDPAL) with applications in low-power circuits. Experimental results show that IDPAL reduces energy usage by 79% compared to equivalent CMOS implementations and by 25% when compared to the best adiabatic implementation. Experiments ranging …

Digital Display With Integrated Computing Circuit, Ronald S. Cok, John W. Harmer, Michael E. Miller

AFIT Patents

A digital display device includes a display substrate; an array of pixels formed on the display substrate; an array of driving circuits located on the display substrate, each driving circuit electrically connected to one or more pixels for controlling a pixel current provided to each pixel; an array of computing circuits located on the display substrate, each computing circuit including circuits for signal or image processing and for communicating with neighboring computing circuits; a plurality of electrical conductors formed on the display substrate and connected to each of the driving circuits and digital computing circuits, wherein each computing circuit is …

Modeling And Architectural Simulations Of The Statistical Static Timing Analysis Of The Variation Sources For Vlsi Circuits, Abu M. Baker

College of Engineering: Graduate Celebration Programs

As CMOS technology scales down, process variation introduces significant uncertainty in power and performance to VLSI circuits and significantly affects their reliability. Although Static-Timing Analysis (STA) remains an excellent tool, current trends in process scaling have imposed significant difficulties to STA. As one of the promising solutions, Statistical static timing analysis (SSTA) has become the frontier research topic in recent years in combating such variation effects. This poster will be focusing on two aspects of SSTA and its applications in VLSI designs: (1) Statistical timing modeling and analysis; and (2) Architectural implementations of the atomic operations (max and add) using …

Asynchronous Mips Processors: Educational Simulations, Robert L. Webb

Master's Theses

The system clock has been omnipresent in most mainstream chip designs. While simplifying many design problems the clock has caused the problems of clock skew, high power consumption, electromagnetic interference, and worst-case performance. In recent years, as the timing constraints of synchronous designs have been squeezed ever tighter, the efficiencies of asynchronous designs have become more attractive. By removing the clock, these issues can be mitigated. How- ever, asynchronous designs are generally more complex and difficult to debug. In this paper I discuss the advantages of asynchronous processors and the specifics of some asynchronous designs, outline the roadblocks to asynchronous …

Unidirectional Cordic For Efficient Computation Of Trigonometric And Hyperbolic Functions, Satish Ravichandran

Electrical & Computer Engineering Theses & Dissertations

CORDIC (Coordinate Rotation Digital Computer) is an iterative algorithm to compute values of trigonometric, logarithmic and transcendental functions by performing vector rotations, which can be implemented with only shift and add operations in a digital system. CORDIC algorithms are extensively used in the areas of digital signal processing, digital image processing and artificial neural networks. A new technique, named unidirectional CORDIC, for efficient computation of trigonometric and hyperbolic functions is presented in this thesis. In the conventional CORDIC algorithm, the vector rotations are performed in both clockwise and counterclockwise directions, but in the unidirectional CORDIC the vectors are rotated only …

Parallel Implementation Of A Face Recognition [Sic] System Based On Modular Pca Approach, Rajkiran Gottumukkal

Electrical & Computer Engineering Theses & Dissertations

This thesis describes research in automated methods for the recognition of human faces. The research is driven by the need to design a method, which would ensure high accuracy under the conditions of facial expression, illumination and pose variations. The resulting method is able to cope with uncontrolled nature of facial expression, illumination and head rotations. The main novelty of this work is the idea that some of the local facial features do not vary even when the facial expression, illumination and pose vary. This idea is applied to the existing principle component analysis lPCA) method to arrive at a …

On The Area Of Hypercube Layouts, Ronald I. Greenberg, Lee Guan

Computer Science: Faculty Publications and Other Works

This paper precisely analyzes the wire density and required area in standard styles for the hypercube. It shows that the most natural, regular layout of a hypercube of N^2 nodes in the plane, in a NxN grid arrangement, uses floor(2N/3)+1 horizontal wiring tracks for each row of nodes. (In the process, we see that the number of tracks per row can be reduced by 1 with a less regular design, as can also be seen from an independent argument of Bezrukov et al.) This paper also gives a simple formula for the wire density at any cut position and a …

A Vhdl Implementation Of Bist Technique In Uart Design, Mohd. Yamani Idna Idris

Student Works (2000-2009)

No abstract provided.