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Full-Text Articles in Systems and Communications

Algorithm Optimization And Hardware Acceleration For Machine Learning Applications On Low-Energy Systems, Jianchi Sun Aug 2022

Algorithm Optimization And Hardware Acceleration For Machine Learning Applications On Low-Energy Systems, Jianchi Sun

All Dissertations

Machine learning (ML) has been extensively employed for strategy optimization, decision making, data classification, etc. While ML shows great triumph in its application field, the increasing complexity of the learning models introduces neoteric challenges to the ML system designs. On the one hand, the applications of ML on resource-restricted terminals, like mobile computing and IoT devices, are prevented by the high computational complexity and memory requirement. On the other hand, the massive parameter quantity for the modern ML models appends extra demands on the system's I/O speed and memory size. This dissertation investigates feasible solutions for those challenges with software-hardware …


Delay Extraction Based Equivalent Elmore Model For Rlc On-Chip Interconnects, Shamsul Arefin Siddiqui Aug 2012

Delay Extraction Based Equivalent Elmore Model For Rlc On-Chip Interconnects, Shamsul Arefin Siddiqui

Electronic Thesis and Dissertation Repository

As feature sizes for VLSI technology is shrinking, associated with higher operating frequency, signal integrity analysis of on-chip interconnects has become a real challenge for circuit designers. For this purpose, computer-aided-design (CAD) tools are necessary to simulate signal propagation of on-chip interconnects which has been an active area for research. Although SPICE models exist which can accurately predict signal degradation of interconnects, they are computationally expensive. As a result, more effective and analytic models for interconnects are required to capture the response at the output of high speed VLSI circuits. This thesis contributes to the development of efficient and closed …


Vlsi Implementation Of High Resolution High Speed Low Latency Pipeline Floating Point Adder/Subtractor For Fft Applications, Rozita Teymourzadeh, Burhan Yeop Majlis, Mok Vh, Masuri Othman Dec 2008

Vlsi Implementation Of High Resolution High Speed Low Latency Pipeline Floating Point Adder/Subtractor For Fft Applications, Rozita Teymourzadeh, Burhan Yeop Majlis, Mok Vh, Masuri Othman

Dr. Rozita Teymourzadeh, CEng.

This paper presents on-chip implementation of high speed low latency floating point adder /subtractor with high accuracy performance for FFT in OFDM transceiver. However due to high performance and high resolution, the floating point adder is matched with power network applications as well. The design was implemented for 32-bit pipelined adder/subtractor which satisfied IEEE-754 Standard for floating -point Arithmetic. The design is focused on the trade-off between the latency and speed improvement as well as resolution and silicon area for the chip implementation. In order to reduce the critical path and decrease the latency, the novel structure was designed and …


Vlsi Implementation Of High Speed And High Resolution Fft Algorithm Based On Radix 2 For Dsp Application, Nooshin Mahdavi, Rozita Teymourzadeh, Masuri Othman Dec 2006

Vlsi Implementation Of High Speed And High Resolution Fft Algorithm Based On Radix 2 For Dsp Application, Nooshin Mahdavi, Rozita Teymourzadeh, Masuri Othman

Dr. Rozita Teymourzadeh, CEng.

Using Fast Fourier Transform (FFT) is indispensable in most signal processing applications. Designing an appropriate algorithm for the implementation of FFT can be efficacious in digital signal processing. Sophisticated techniques such as pipelining and parallel calculations have potential impacts on VLSI implementation of FFT algorithm. Furthermore, a mathematic approach such as floating point calculation achieves higher precision. In this paper, an efficient algorithm with using parallel and pipelining methods is proposed to implement high speed and high resolution FFT algorithm. Latency reduction is an important issue to implement the high speed FFT on FPGA. The Proposed FFT algorithm shows the …