Systems and Communications Commons^™

Reference Design Of An Online Emulation And Hot-Patching Approach For Power Electronic Controller Validation, Estefano Soria Pearson

Graduate Theses and Dissertations

This thesis aims to develop a reference design of an online security system approach embedded in a power electronic controller for cybersecurity purposes. Cybersecurity in power electronics focuses on reducing vulnerabilities in the system, where most reside in the communication with the hardware devices. Although methods to secure communications lessen the probability and effects of cyber-attacks, discovering vulnerabilities is inevitable. This thesis attempts to provide a fail-safe approach to securing the system by targeting the safety of the power-electronic controller. This approach applies an additional security layer in case of a malicious or accidental controller firmware malfunction.

The online security …

Short-Circuit Protection For Low-Voltage Dc Distribution Systems Based On Solid-State Circuit Breakers, Sharthak Munasib

Graduate Theses and Dissertations

Proper short-circuit protection in dc distribution systems has provided an austere challenge to researchers as the development of commercially-viable equipment providing fast operation, coordination and reliability still continues. The objective of this thesis is to analyze issues associated with short-circuit protection of low-voltage dc (LVDC) distribution systems and propose a short-circuit protection methodology based on solid-state circuit breakers (SSCBs) that provides fault-current limiting (FCL). Simulation results for a simplified notional 1-kVdc distribution system, performed in MATLAB/SIMULINKTM, would be presented to illustrate that SSCB solutions based on reverse-blocking integrated gate-commutated thyristors (RB-IGCT) are feasible for low-voltage dc distribution systems but requires …

Design And Analysis Of An Adaptive Asynchronous System Architecture For Energy Efficiency, Brent Michael Hollosi

Graduate Theses and Dissertations

Power has become a critical design parameter for digital CMOS integrated circuits. With performance still garnering much concern, a central idea has emerged: minimizing power consumption while maintaining performance. The use of dynamic voltage scaling (DVS) with parallelism has shown to be an effective way of saving power while maintaining performance. However, the potency of DVS and parallelism in traditional, clocked synchronous systems is limited because of the strict timing requirements such systems must comply with. Delay-insensitive (DI) asynchronous systems have the potential to benefit more from these techniques due to their flexible timing requirements and high modularity. This dissertation …