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Evaluation And Analysis Of Null Convention Logic Circuits, John Davis Brady Dec 2019

Evaluation And Analysis Of Null Convention Logic Circuits, John Davis Brady

Graduate Theses and Dissertations

Integrated circuit (IC) designers face many challenges in utilizing state-of-the-art technology nodes, such as the increased effects of process variation on timing analysis and heterogeneous multi-die architectures that span across multiple technologies while simultaneously increasing performance and decreasing power consumption. These challenges provide opportunity for utilization of asynchronous design paradigms due to their inherent flexibility and robustness.

While NULL Convention Logic (NCL) has been implemented in a variety of applications, current literature does not fully encompass the intricacies of NCL power performance across a variety of applications, technology nodes, circuit scale, and voltage scaling, thereby preventing further adoption and utilization …


Model Development And Assessment Of The Gate Network In A High-Performance Sic Power Module, William Austin Curbow May 2019

Model Development And Assessment Of The Gate Network In A High-Performance Sic Power Module, William Austin Curbow

Graduate Theses and Dissertations

The main objective of this effort is to determine points of weakness in the gate network of a high-performance SiC power module and to offer remedies to these issues to increase the overall performance, robustness, and reliability of the technology. In order to accomplish this goal, a highly accurate model of the gate network is developed through three methods of parameter extraction: calculation, simulation, and measurement. A SPICE model of the gate network is developed to analyze four electrical issues in a high-speed, SiC-based power module including the necessary internal gate resistance for damping under-voltage and over-voltage transients, the disparity …