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Articles 1 - 29 of 29
Full-Text Articles in Electrical and Computer Engineering
Synthesis Of Reversible Circuits For Large Reversible Functions, Marek Perkowski, Nouraddin Alhagi, Maher Hawash
Synthesis Of Reversible Circuits For Large Reversible Functions, Marek Perkowski, Nouraddin Alhagi, Maher Hawash
Electrical and Computer Engineering Faculty Publications and Presentations
This paper presents a new algorithmMP (multiple pass) to synthesize large reversible binary circuits without ancilla bits. The well-known MMD algorithm for synthesis of reversible circuits requires to store a truth table (or a Reed-Muller - RM transform) as a 2n vector to represent a reversible function of n variables. This representation prohibits synthesis of large functions. However, in MP we do not store such an exponentially growing data structure. The values of minterms are calculated in MP dynamically, one-by-one, from a set of logic equations that specify the reversible circuit to be designed. This allows for synthesis of large …
A Study Of The Lyapunov Stability Of An Open-Loop Induction Machine, Ahmed Oteafy, John Chiasson
A Study Of The Lyapunov Stability Of An Open-Loop Induction Machine, Ahmed Oteafy, John Chiasson
Electrical and Computer Engineering Faculty Publications and Presentations
The induction motor is widely utilized in industry and exists in a plethora of applications. Until the last 20 years or so, it was primarily used in an open-loop fashion (i.e., balanced sinusoidal voltages, constant load torque and viscous friction) with its inherent stability counted on to allow operation over a wide range of operating conditions. Unlike classical arguments based on the steady-state torque-slip curve, a rigorous analytical stability argument using the full nonlinear dynamical model is presented. In particular, conditions for global asymptotic stability of the induction motor in the sense of Lyapunov are given in terms of the …
Cavity Resonant Mode In A Metal Film Perforated With Two-Dimensional Triangular Lattice Hole Arrays, Wan Kuang, Alex English, William B. Knowlton, Jeunghoon Lee, William L. Hughes, Bernard Yurke
Cavity Resonant Mode In A Metal Film Perforated With Two-Dimensional Triangular Lattice Hole Arrays, Wan Kuang, Alex English, William B. Knowlton, Jeunghoon Lee, William L. Hughes, Bernard Yurke
Electrical and Computer Engineering Faculty Publications and Presentations
The transmission property of metallic films with two-dimensional hole arrays is studied experimentally and numerically. For a triangular lattice subwavelength hole array in a 150 nm thick Ag film, both cavity resonance and planar surface modes are identified as the sources of enhanced optical transmissions. Semi-analytical models are developed for calculating the dispersion relation of the cavity resonant mode. They agree well with the experimental results and full-wave numerical calculations. Strong interaction between the cavity resonant mode and surface modes is also observed.
Silver Chalcogenide Based Memristor Devices, Antonio S. Oblea, Achyut Timilsina, David Moore, Kristy A. Campbell
Silver Chalcogenide Based Memristor Devices, Antonio S. Oblea, Achyut Timilsina, David Moore, Kristy A. Campbell
Electrical and Computer Engineering Faculty Publications and Presentations
We have fabricated two-terminal chalcogenide-based devices containing Ge2Se3 and Ag that function as memristors. These devices have been electrically characterized at room temperature using quasi-static DC methods, AC sinusoidal methods, and AC pulse testing methods. In all cases, the devices exhibit memristive behavior.
Absolute Blood Velocity Measured With A Modified Fundus Camera, Donald D. Duncan, Paul Lemaillet, Mohamed Ibrahim, Quan D. Nguyen, Matthias Hiller, Jessica C. Ramella-Roman
Absolute Blood Velocity Measured With A Modified Fundus Camera, Donald D. Duncan, Paul Lemaillet, Mohamed Ibrahim, Quan D. Nguyen, Matthias Hiller, Jessica C. Ramella-Roman
Electrical and Computer Engineering Faculty Publications and Presentations
We present a new method for the quantitative estimation of blood flow velocity, based on the use of the Radon transform. The specific application is for measurement of blood flow velocity in the retina. Our modified fundus camera uses illumination from a green LED and captures imagery with a high-speed CCD camera. The basic theory is presented, and typical results are shown for an in vitro flow model using blood in a capillary tube. Subsequently, representative results are shown for representative fundus imagery. This approach provides absolute velocity and flow direction along the vessel centerline or any lateral displacement therefrom. …
Joint Loop End Modeling Improves Covariance Model Based Non-Coding Rna Gene Search, Jennifer Smith
Joint Loop End Modeling Improves Covariance Model Based Non-Coding Rna Gene Search, Jennifer Smith
Electrical and Computer Engineering Faculty Publications and Presentations
The effect of more detailed modeling of the interface between stem and loop in non-coding RNA hairpin structures on efficacy of covariance-model-based non-coding RNA gene search is examined. Currently, the prior probabilities of the two stem nucleotides and two loop-end nucleotides at the interface are treated the same as any other stem and loop nucleotides respectively. Laboratory thermodynamic studies show that hairpin stability is dependent on the identities of these four nucleotides, but this is not taken into account in current covariance models. It is shown that separate estimation of emission priors for these nucleotides and joint treatment of substitution …
Application Of Cuda In The Boolean Domain For The Unate Covering Problem, Eric Paul, Bernd Steinbach, Marek Perkowski
Application Of Cuda In The Boolean Domain For The Unate Covering Problem, Eric Paul, Bernd Steinbach, Marek Perkowski
Electrical and Computer Engineering Faculty Publications and Presentations
NVIDIA’s Compute Unified Device Architecture (CUDA) is a relatively-recent development that allows to realize very fast algorithms for several Constraint Satisfaction and Computer Aided Design tasks. In this paper we present an approach to use Graphics Processing Units (GPU) and CUDA for solving Unate Covering Problem, a practical problem related to SAT. In particular we present a CUDA-enabled Petrick Function Minimizer. We compare the performance of a pipeline-processor (CPU) and a parallel processor (GPU) implementation of the matrix-multiplication method for solving unate covering problems.
Synthesis Of Higher-Order K-Delta-1-Sigma Modulators For Wideband Adcs, Vishal Saxena, R. Jacob Baker
Synthesis Of Higher-Order K-Delta-1-Sigma Modulators For Wideband Adcs, Vishal Saxena, R. Jacob Baker
Electrical and Computer Engineering Faculty Publications and Presentations
As CMOS technology shrinks, the transistor speed increases enabling higher speed communications and more complex systems. These benefits come at the cost of decreasing inherent device gain, increased transistor leakage currents and device mismatches due to process variations. All of these drawbacks affect the design of high-resolution analog-to-digital converters (ADCs) in nano-CMOS processes. To move towards an ADC topology useful in nano-CMOS, the K-Delta-1-Sigma (KD1S) modulator-based ADC was proposed. This paper extends the KD1S to higher order topologies using a systematic synthesis procedure. Second and third order KD1S modulator are designed and simulated to demonstrate the synthesis method.
Indirect Compensation Techniques For Three-Stage Fully-Differential Op-Amps, Vishal Saxena, R. Jacob Baker
Indirect Compensation Techniques For Three-Stage Fully-Differential Op-Amps, Vishal Saxena, R. Jacob Baker
Electrical and Computer Engineering Faculty Publications and Presentations
As CMOS technology continues to evolve, the
supply voltages are decreasing while at the same time the transistor threshold voltages are remaining relatively constant. Making matters worse, the inherent gain available from the nano-CMOS transistors is dropping. Traditional techniques for achieving high-gain by cascoding become less useful in nano-scale CMOS processes. Horizontal cascading (multi-stage) must be used in order to realize high-gain op-amps in low supply voltage processes. This paper discusses indirect compensation techniques for op-amps using split-length devices. A reversed-nested indirect compensated (RNIC) topology, employing double pole-zero cancellation, is illustrated for the design of three-stage op-amps. The RNIC topology …
Experimental Observations Of Active Invariance Striations In A Tank Environment, Jorge E. Quijano, Richard L. Campbell, Tobias G. Oesterlein, Lisa M. Zurk
Experimental Observations Of Active Invariance Striations In A Tank Environment, Jorge E. Quijano, Richard L. Campbell, Tobias G. Oesterlein, Lisa M. Zurk
Electrical and Computer Engineering Faculty Publications and Presentations
The waveguide invariant in shallow water environments has been widely studied in the context of passive sonar. The invariant provides a relationship between the frequency content of a moving broadband source and the distance to the receiver, and this relationship is not strongly affected by small perturbations in environment parameters such as sound speed or bottom features. Recent experiments in shallow water suggest that a similar range-frequency structure manifested as striations in the spectrogram exists for active sonar, and this property has the potential to enhance the performance of target tracking algorithms. Nevertheless, field experiments with active sonar have not …
A Reconfigurable Pattern Matching Hardware Implementation Using On-Chip Ram-Based Fsm, Nader I. Rafla, Indrawati Gauba
A Reconfigurable Pattern Matching Hardware Implementation Using On-Chip Ram-Based Fsm, Nader I. Rafla, Indrawati Gauba
Electrical and Computer Engineering Faculty Publications and Presentations
The use of synthesizable reconfigurable IP cores has increasingly become a trend in System on Chip (SoC) designs because of their flexibility and powerful functionality. The market introduction of multi-featured platform FPGAs equipped with embedded memory and processor blocks has further expanded the possibility of utilizing dynamic reconfiguration to improve overall system adaptability to meet varying product requirements. In this paper, a reconfigurable hardware implementation for pattern matching using Finite State machine (FSM) is proposed. The FSM design is RAMbased and is reconfigured on the fly through altering memory contents only. An embedded processor is used for orchestrating run time …
Evolutionary Quantum Logic Synthesis Of Boolean Reversible Logic Circuits Embedded In Ternary Quantum Space Using Heuristics, Martin Lukac, Marek Perkowski, Michitaka Kameyama
Evolutionary Quantum Logic Synthesis Of Boolean Reversible Logic Circuits Embedded In Ternary Quantum Space Using Heuristics, Martin Lukac, Marek Perkowski, Michitaka Kameyama
Electrical and Computer Engineering Faculty Publications and Presentations
It has been experimentally proven that realizing universal quantum gates using higher-radices logic is practically and technologically possible. We developed a Parallel Genetic Algorithm that synthesizes Boolean reversible circuits realized with a variety of quantum gates on qudits with various radices. In order to allow synthesizing circuits of medium sizes in the higher radix quantum space we performed the experiments using a GPU accelerated Genetic Algorithm. Using the accelerated GA we compare heuristic improvements to the mutation process based on cost minimization, on the adaptive cost of the primitives and improvements due to Baldwinian vs. Lamarckian GA.We also describe various …
Software Defined Radio: Inexpensive Hardware And Software Tools, Thad B. Welch, Cameron H. G Wright, Michael G. Morrow
Software Defined Radio: Inexpensive Hardware And Software Tools, Thad B. Welch, Cameron H. G Wright, Michael G. Morrow
Electrical and Computer Engineering Faculty Publications and Presentations
DSP topics such as software defined radio are more easily taught if appropriate demonstrations and laboratory experiences are provided. This paper describes a new, inexpensive software defined radio educational platform based upon MATLAB and the Texas Instruments C6713 digital signal processing starter kit. We describe the hardware and software issues and briefly describe recommended classroom use.
Compact Method For Modeling And Simulation Of Memristor Devices: Ion Conductor Chalcogenide-Based Memristor Devices, Kristy A. Campbell, Antonio Oblea, Achyut Timilsina
Compact Method For Modeling And Simulation Of Memristor Devices: Ion Conductor Chalcogenide-Based Memristor Devices, Kristy A. Campbell, Antonio Oblea, Achyut Timilsina
Electrical and Computer Engineering Faculty Publications and Presentations
A compact model and simulation methodology for chalcogenide based memristor devices is proposed. From a microprocessor design view point, it is important to be able to simulate large numbers of devices within the integrated circuit architecture in order to speed up reliably the development process. Ideally, device models would accurately describe the characteristic device behavior and would be represented by single-valued equations without requiring the need for recursive or numerically intensive solutions. With this in mind, we have developed an empirical chalcogenide compact memristor model that accurately describes all regions of operations of memristor devices employing single-valued equations.
An Analysis Of Binarization Ground Truthing, Elisa H. Barney Smith
An Analysis Of Binarization Ground Truthing, Elisa H. Barney Smith
Electrical and Computer Engineering Faculty Publications and Presentations
The accuracy of a binarization algorithm is often calculated relative to a ground truth image. Except for synthetically generated images, no ground truth image exists. Evaluating binarization on real images is preferred. The ground truthing between and among different operators is compared. Four direct metrics were used. The variability of the results of five different automatic binarization algorithms were compared to that of manual ground truth results. Significant variability in the ground truth results was found.
Case Study Of Finite Resource Optimization In Fpga Using Genetic Algorithm, Jingxia Wang, Sin Ming Loo
Case Study Of Finite Resource Optimization In Fpga Using Genetic Algorithm, Jingxia Wang, Sin Ming Loo
Electrical and Computer Engineering Faculty Publications and Presentations
Modem Field-Programmable Gate Arrays (FPGAs) are becoming very popular in embedded systems and high performance applications. FPGA has benefited from the shrinking of transistor feature size, which allows more on-chip reconfigurable (e.g., memories and look-up tables) and routing resources available. Unfortunately, the amount of reconfigurable resources in a FPGA is fixed and limited. This paper investigates the mapping scheme of the applications in a FPGA by utilizing sequential processing (e.g., Altera Nios II or Xilinx Microblaze, using C programming language) and task specific hardware (using hardware description language). Genetic Algorithm is used in this study. We found that placing sequential …
Optimizing Reconfigurable Hardware Resource Usage In System-On-A-Programmable-Chip With Location-Aware Genetic Algorithm, Sin Ming Loo, Jingxia Wang
Optimizing Reconfigurable Hardware Resource Usage In System-On-A-Programmable-Chip With Location-Aware Genetic Algorithm, Sin Ming Loo, Jingxia Wang
Electrical and Computer Engineering Faculty Publications and Presentations
This paper presents static task scheduling using location-aware genetic algorithm techniques to schedule task systems to finite amounts of reconfigurable hardware. This research optimizes the use of limited reconfigurable resources. This scheduling algorithm is built upon our previous work [12- 14]. In this paper, the genetic algorithm has been expanded to include a feature to assign selected tasks to specific functional units. In this reconfigurable hardware environment, multiple sequential processing elements (soft core processors such as Xilinx MicroBlaze [22] or Altera Nios-II [1]), task-specific core (application specific hardware), and communication network within the reconfigurable hardware can be used (such a …
Computation Intelligence Method To Find Generic Non-Coding Rna Search Models, Jennifer A. Smith
Computation Intelligence Method To Find Generic Non-Coding Rna Search Models, Jennifer A. Smith
Electrical and Computer Engineering Faculty Publications and Presentations
Fairly effective methods exist for finding new noncoding RNA genes using search models based on known families of ncRNA genes (for example covariance models). However, these models only find new members of the existing families and are not useful in finding potential members of novel ncRNA families. Other problems with family-specific search include large processing requirements, ambiguity in defining which sequences form a family and lack of sufficient numbers of known sequences to properly estimate model parameters. An ncRNA search model is proposed which includes a collection of non-overlapping RNA hairpin structure covariance models. The hairpin models are chosen from …
Main Memory With Proximity Communication: A Wide I/O Dram Architecture, Qawi Harvard, R. Jacob Baker, Robert Drost
Main Memory With Proximity Communication: A Wide I/O Dram Architecture, Qawi Harvard, R. Jacob Baker, Robert Drost
Electrical and Computer Engineering Faculty Publications and Presentations
The bandwidth and power consumption of dynamic random access memory (DRAM), used as the main memory of a computer system, impacts computer execution rates. DRAM manufacturers focus on density increases, due to the innate price per bit decline of main memory, while processor manufacturers continually focus on boosting performance. This leads to a performance gap between the two technologies. Proximity communication promises to increase the off/on chip bandwidth of DRAM products while reducing the power consumption of the main memory system. The design of a memory system employing 4 Gb DRAM chips with a 64-bit wide communication bus using proximity …
Gain Error Correction For Cmos Image Sensor Using Delta-Sigma Modulation, Kuangming Yap, R. Jacob Baker
Gain Error Correction For Cmos Image Sensor Using Delta-Sigma Modulation, Kuangming Yap, R. Jacob Baker
Electrical and Computer Engineering Faculty Publications and Presentations
A delta-sigma modulation analog-to-digital converter (ADC) has many benefits over the use of a pipeline ADC in a CMOS image sensor. This includes lower power, noise reduction, ease of maximizing the input range, and simpler signal routing for large arrays. Multiple delta-sigma modulation ADC is required in a CMOS image sensor, one for each pixel column. Any voltage threshold mismatch between ADCs will introduce gain and offset error in its transfer function, which will lead to fix pattern noise. Correcting these gain and offset error for every ADCs in the image sensor will require a complex digital signal processor. Therefore, …
Influence Of Cu Diffusion Conditions On The Switching Of Cu-Sio2-Based Resistive Memory Devices, S.C. Puthen Thermadam, S. K. Bhagat, T. L. Alford, Y. Sakaguchi, M. N. Kozicki, Maria Mitkova
Influence Of Cu Diffusion Conditions On The Switching Of Cu-Sio2-Based Resistive Memory Devices, S.C. Puthen Thermadam, S. K. Bhagat, T. L. Alford, Y. Sakaguchi, M. N. Kozicki, Maria Mitkova
Electrical and Computer Engineering Faculty Publications and Presentations
This paper presents a study of Cu diffusion at various temperatures in thin SiO2 films. Film composition and diffusion products were analyzed using Secondary Ion Mass Spectroscopy, Rutherford Backscattering Spectrometry, X-ray Diffraction and Raman Spectroscopy methods. We found a strong dependence of the diffused Cu concentration, which varied between 0.8 at.% and 10-3 at.%, on the annealing temperature. X-ray diffraction and Raman studies revealed that Cu does not react with the SiO2 network and remains in elemental form after diffusion. Programmable Metallization Cell (PMC) resistive memory cells were fabricated with these Cu-diffused SiO2 films as the active …
Adaptive Passive Fathometer Processing, Martin Siderius, Heechun Song, Peter Gerstoft, William S. Hodgkiss, Paul Hursky, Chris H. Harrison
Adaptive Passive Fathometer Processing, Martin Siderius, Heechun Song, Peter Gerstoft, William S. Hodgkiss, Paul Hursky, Chris H. Harrison
Electrical and Computer Engineering Faculty Publications and Presentations
Recently, a technique has been developed to image seabed layers using the ocean ambient noise field as the sound source. This so called passive fathometer technique exploits the naturally occurring acoustic sounds generated on the sea-surface, primarily from breaking waves. The method is based on the cross-correlation of noise from the ocean surface with its echo from the seabed, which recovers travel times to significant seabed reflectors. To limit averaging time and make this practical, beamforming is used with a vertical array of hydrophones to reduce interference from horizontally propagating noise. The initial development used conventional beamforming, but significant improvements …
Design Of Asynchronous Circuits For High Soft Error Tolerance In Deep Submicron Cmos Circuits, Weidong Kuang, Peiyi Zhao, J. S. Yuan, R. F. Demara
Design Of Asynchronous Circuits For High Soft Error Tolerance In Deep Submicron Cmos Circuits, Weidong Kuang, Peiyi Zhao, J. S. Yuan, R. F. Demara
Electrical and Computer Engineering Faculty Publications and Presentations
As the devices are scaling down, the combinational logic will become susceptible to soft errors. The conventional soft error tolerant methods for soft errors on combinational logic do not provide enough high soft error tolerant capability with reasonably small performance penalty. This paper investigates the feasibility of designing quasi-delay insensitive (QDI) asynchronous circuits for high soft error tolerance. We analyze the behavior of null convention logic (NCL) circuits in the presence of particle strikes, and propose an asynchronous pipeline for soft-error correction and a novel technique to improve the robustness of threshold gates, which are basic components in NCL, against …
Multiharmonic Frequency Tracking Method Using The Sigma-Point Kalman Smoother, Sunghan Kim, Anindya S. Paul, Eric A. Wan, James Mcnames
Multiharmonic Frequency Tracking Method Using The Sigma-Point Kalman Smoother, Sunghan Kim, Anindya S. Paul, Eric A. Wan, James Mcnames
Electrical and Computer Engineering Faculty Publications and Presentations
Several groups have proposed the state-space approach to tracking time-varying frequencies of multiharmonic quasiperiodic signals. The extended Kalman filter/smoother (EKF/EKS) is one of the common frequency tracking approaches seen in the literature. We introduce a multiharmonic frequency tracker based on the forward-backward statistical linearized Sigma-Point Kalman smoother (FBSL-SPKS) and compare its performance to that of the extended Kalman smoother (EKS). In all cases the FBSL-SPKS tracker outperformed the EKS tracker over a wide range of signal-to-noise (SNR) ratios. We also demonstrate its superior performance on real signals.
Relating Electrophotographic Printing Model And Is013660 Standard Attributes, Elisa H. Barney Smith
Relating Electrophotographic Printing Model And Is013660 Standard Attributes, Elisa H. Barney Smith
Electrical and Computer Engineering Faculty Publications and Presentations
A mathematical model of the electrophotographic printing process has been developed. This model can be used for analysis. From this a print simulation process has been developed to simulate the effects of the model components on toner particle placement. A wide variety of simulated prints are produced from the model's three main inputs, laser spread, charge to toner proportionality factor and toner particle size. While the exact placement of toner particles is a random process, the total effect is not. The effect of each model parameter on the ISO 13660 print quality attributes line width, fill, raggedness and blurriness is …
2x1d Image Registration And Comparison, Geng Zheng, Elisa H. Barney Smith, Nader Rafla, Tim Andersen
2x1d Image Registration And Comparison, Geng Zheng, Elisa H. Barney Smith, Nader Rafla, Tim Andersen
Electrical and Computer Engineering Faculty Publications and Presentations
This paper presents a novel 2x1D phase correlation based image registration method for verification of printer emulator output. The method combines the basic phase correlation technique and a modified 2x1D version of it to achieve both high speed and high accuracy. The proposed method has been implemented and tested using images generated by printer emulators. Over 97% of the image pairs were registered correctly, accurately dealing with diverse images with large translations and image cropping.
Document Analysis Issues In Reading Optical Scan Ballots, Daniel Lopresti, George Nagy, Elisa H. Barney Smith
Document Analysis Issues In Reading Optical Scan Ballots, Daniel Lopresti, George Nagy, Elisa H. Barney Smith
Electrical and Computer Engineering Faculty Publications and Presentations
Optical scan voting is considered by many to be the most trustworthy option for conducting elections because it provides an independently verifiable record of each voter’s intent. While op-scan technology has been in use for decades, attempts to improve the machine-reading of ballots raise a range of interesting issues in document image analysis. Work thus far has been hindered by a lack of real-world data, however, since ballots associated with actual elections are kept secure from the public and normally destroyed after a period time. Fortunately, as a result of a recent challenged federal election in Minnesota, a large number …
Effect Of Pre-Processing On Binarization, Elisa Barney Smith, Laurence Likforman-Sulem, Jérôme Darbon
Effect Of Pre-Processing On Binarization, Elisa Barney Smith, Laurence Likforman-Sulem, Jérôme Darbon
Electrical and Computer Engineering Faculty Publications and Presentations
The effects of different image pre-processing methods for document image binarization are explored. They are compared on five different binarization methods on images with bleed through and stains as well as on images with uniform background speckle. The binarization method is significant in the binarization accuracy, but the pre-processing also plays a significant role. The Total Variation method of pre-processing shows the best performance over a variety of pre-processing methods.
Fault Testing Quantum Switching Circuits, Marek Perkowski, Jacob Biamonte
Fault Testing Quantum Switching Circuits, Marek Perkowski, Jacob Biamonte
Electrical and Computer Engineering Faculty Publications and Presentations
Test pattern generation is an electronic design automation tool that attempts to find an input (or test) sequence that, when applied to a digital circuit, enables one to distinguish between the correct circuit behavior and the faulty behavior caused by particular faults. The effectiveness of this classical method is measured by the fault coverage achieved for the fault model and the number of generated vectors, which should be directly proportional to test application time. This work address the quantum process validation problem by considering the quantum mechanical adaptation of test pattern generation methods used to test classical circuits. We found …