Engineering Commons^™

Uniformity Correction For Infrared Ir-Ccd Camera, Chien-Ming Leng

Theses

This thesis describes the results of a study of three types of uniformity correction schemes for an infrared camera. More specifically, a Datacube Image System was used to simulate the three uniformity correction schemes for a 320x244-element IR-CCD TV camera with PtSi Schottky-barrier detectors. The three uniformity correction schemes are: one-point uniformity correction with single background, one-point uniformity correction with multibackground and two-point uniformity correction. Datacube programs were developed for the three above uniformity correction schemes and some experimental results were obtained.

The Bandwidth Allocation Of Atm Through Genetic Algorithm, Hong Pan

Theses

In this thesis, we develop an optimization method based on Genetic Algorithm to achieve the bandwidth allocation of ATM network. In Broadband Integrated Service Digital Network (BISDN), the Asynchronous Transfer Model (ATM) is already adopted as the transfer standard by CCITT. ATM is a high-bandwidth, low-delay, fast-packet switching and multiplexing technique. Using ATM technique, we can flexibly reconfigure the network and reassign the bandwidth to meet the requirement of all types of services. As an effective optimization method, Genetic Algorithm(GA) is applied to implement the bandwidth allocation of ATM. GA is a class of search algorithm based on the mechanics …

Artificial Dielectric Polymeric Optical Waveguides, Peng Chen

Theses

Wave propagation in artificial dielectric polymeric optical thin film waveguides is studied. These artificial dielectric films are made of multiple layers either metallic or semiconductor clusters in polymeric matrix. The waveguides are fabricated using the plasma polymerization and vacuumm evaporation deposition method. By analyzing results of these kinds of structures, some important conclusions can be obtained. The artificial dielectric layer in the waveguide center effectively changes the modal distribution in the waveguides. In the case of semiconductor layer, an all optical switch may be realized.

Information Handling System With A Personal Computer To Assist In The Manufacturing Of Plastic Parts, Yi Chung

Theses

The ongoing personal computer development has led to its increasing application in manufacturing to improve productivity. Being more aware of this technology, most of these benefits have accrued to large firms. The intent of this thesis is to show that it is equally advantageous for small manufacturing companies to utilize them and show how they can do so.

The field of production control systems is discussed and those areas where personal computers can be applied are emphasized. Forecasting, warehouse management, material requirement planning, and inventory control are the most appropriate. An application example using dBase III plus to write the …

Hybrid Wafer Scale Microcircuit Integration -- [ 4989063 ], Edward S. Kolesar Jr.

AFIT Patents

A wafer scale integration arrangement wherein integrated circuit die of varying size, fabrication processes, and function are commonly mounted in the same host wafer using a filled epoxy material of special characteristics. The mounting epoxy material also serves as a substrate for the die interconnecting conductors in regions adjacent the mounted die. The described assembly also includes a newly available photosensitive polyimide material as a planarization and passivation covering for the die and host wafer and as a mounting surface for an interconnecting metal conductor array. Multiple levels of interconnection metal. Fabrication processes for the die to host wafer attachment …

Method For Treating Wood Against Fungal Attack, Peter E. Laks

Michigan Tech Patents

Complexes of sulfited tannin extract and a copper(II) ion effectively protect wood against fungal attack. The complex can be impregnated into wood in a single step treatment using a water/organic solvent system, or formed in situ by treating the wood with an aqueous solution containing the extract and subsequently treating the wood with an aqueous solution containing a copper (II) salt.

Lrfd Cold-Formed Steel Design Manual, American Iron And Steel Institute

American Iron and Steel Institute (AISI) Specifications, Standards, Manuals and Research Reports (1946 - present)

No abstract provided.

Simplified Cost Models For Prefeasibility Mineral Evaluations. U.S. Bureau Of Mines Information Circular 9298, 35, Thomas W. Camm

Mining Engineering

In this U.S. Bureau of Mines report, mine and mill cost models are presented to make quick estimates of the cost to develop mineral deposits in the desert region of the Southwest United States. Regression analysis was used to generate capital and operating cost equations for each model in the form Y = AXB, where Y is the cost estimated and X is the assumed daily capacity in short tons. A and B are constants determined by the regression analysis. Each is broken down into 11 subcategories to facilitate escalation of costs for inflation and to increase their versatility in …

Wright State University College Of Engineering And Computer Science Bits And Pcs Newsletter, January 1991, College Of Engineering And Computer Science, Wright State University

BITs and PCs Newsletter

A twelve page newsletter created by the Wright State University College of Engineering and Computer Science that addresses the current affairs of the college.

The Use Of Expert Systems In Demand Forecasting, Edward Sweeney

Books/Book chapters

No abstract provided.

The Added Mass, Basset, And Viscous Drag Coefficients In Nondilute Bubbly Liquids Undergoing Small-Amplitude Oscillatory Motion, Ashok S. Sangani, D. Z. Zhang, A. Prosperetti

Biomedical and Chemical Engineering - All Scholarship

The motion of bubbles dispersed in a liquid when a small-amplitude oscillatory motion is imposed on the mixture is examined in the limit of small frequency and viscosity. Under these conditions, for bubbles with a stress-free surface, the motion can be described in terms of added mass and viscous force coefficients. For bubbles contaminated with surface-active impurities, the introduction of a further coeflicient to parametrize the Basset force is necessary. These coefficients are calculated numerically for random configurations of bubbles by solving the appropriate multibubble interaction problem exactly using a method of multipole expansion. Results obtained by averaging over several …

Multilevel Metalization, Michael J. Bailey

Journal of the Microelectronic Engineering Conference

A bilevel metallization process using aluminum with 1~ silicon for the Metal 1 layer, pure aluminum for the Metal 2 layer, and Accuglass X-11 311 Series spin-on glass for the interlevel dielectric was investigated. Problems encountered in via etching with previous bilevel work were eliminated by using a modified buffered HF etchant. Vias down to 6x6um in size were found to conduct and have resistances less than 1 Ohm. Spin-on glass coating processes, however, were still in need of refinement, as numerous pinholes were observed over the aluminum regions.

A Comparison Between Resist Hardening Using A Conformable Mold And Plasma Resist Image Stabilization: Techniques To Enhance Resist Thermal Stability, Kathleen M. Brown

Journal of the Microelectronic Engineering Conference

KTI-820, a positive photoresist was hardened utilizing two different methods. The PRIST technique involved the exposure of the patterned resist to a plasma containing CF4 plus Helium followed by a 210C, 30 mm postbake. The RHCM technique involved the encapsulation of the patterned resist with a PMMA mold followed by a 210C, 30 mm postbake and subsequent PMMA removal. The performance of hardened structures on multilayer substrates was investigated for both dry etching and ion implantation processes. The results indicate that the RHCM technique is the superior method. Scanning electron micrographs showed a minimum amount of pattern distortion while nanoline …

Design Of A 4-Bit Microprocessor, Hsiao-Hui Miguel Chen

Journal of the Microelectronic Engineering Conference

A four bit microprocessor’s layout was drawn on an Apollo workstation using MOSIS two lambda design rules. The layout’s operation was verified by breadboarding with 74’00 HCMOS logic parts during Spring Quarter 1990 by Theodore D’Antonoli. Based on his findings, the layout was revised and several design changes were added. At the same time, a software simulation program (uPROSIM) for the processor was written in FORTRAN on the RIT VMS Computer System.

Design And Fabrication Of Five Microns Nmos Sram, Robert Chizmadia

Journal of the Microelectronic Engineering Conference

A 126 bit by one bit NMDS static RAM was designed following design rules for RIT’s standard four layer NMDS process. Verification of working devices was done using the SPICE circuit simulator, but some concerns exist with this because of assumptions made in model parameters. Fabrication was an intended goal of this project, but time restraints allowed only masks to be made.

An Ellipsometeric Evaluation Of Ion Implanted Silicon, Patrick G. Drennan

Journal of the Microelectronic Engineering Conference

~ Split Split Plot Design was implemented to investigate the relationship between the ion implantation conditions and the complex refractive index of the inherent damage layer. Four factors chosen to evaluate this relationship were wafer orientation, dose concentration, implant acceleration potential, and screen oxide thickness. The response variable was the complex refractive index of the damaged layer measured by ellipsometry. Results indicate that there is a relationship between the dose concentration and the response variable that is most sensitive to doses between 5e13 ions/cm2 and 5e15 ions/cm2. However, the range of the refractive index increases considerably in this range to …

Energy Dispersive Spectroscopy X-Ray Microanalysis, Jim Eun

Journal of the Microelectronic Engineering Conference

An overview or Energy Dispersive Spectroscopy (EDS) X-ray microanalysis is presented with attention to artifacts present in the X—ray spectrum, such as the Bremsstrahlung, sum peaks, and silicon escape peaks. Sample spectra obtained from Al on Si, Cu on 51, and PZT ferroelectric films demonstrated the capability of obtaining qualitative elemental composition. The elemental spatial distribution, or the X—ray mapping. capability was also demonstrated utilizing a special alloy sample.

Integration Of Cad Data Transcription For E-Beam Lithography, Ian David Fink

Journal of the Microelectronic Engineering Conference

A software system for preparing data for e-beam mask making called Computer Aided Transcription Software is described. In order to appreciate its capabilities, an overview of writing requirements for a MEBES I e-beam tool are given. Sample files and software output are provided to illustrate the concepts.

A Drm Study Of Microposit Sal603 Resist In Developers Of Different Normality, Kimberly A. Guggemos

Journal of the Microelectronic Engineering Conference

Microposit SAL6O3, a negative working chemically amplified electron beam resist, was studied for four developers of different normality: Microposit MF322 (0.266 N), MF321 (0.210 N), MF320 (0.255 N), or MF319 (0.237 N). Wafers were exposed to create eight regions, each with incrementally increasing exposure. Development in each of the eight zones was monitored simultaneously with a Perkin Elmer 5900 Development Rate Monitor (DRM). Increased developer normality was shown to increase development rate and photoresist contrast, but decreased sensitivity.

Characterization And Process Development For The Mebes I Electron Beam Lithography System, Richard D. Holscher

Journal of the Microelectronic Engineering Conference

Characterization of a MEBES I electron beam lithography tool was done to investigate electron bear writing errors induced by electrical and mechanical interactions of the system. Process development of SAL6O3 a negatively working chemically amplified resist, which is required to provide a high sensitivity repeatable resist film, was also done.

Evaluation Of A Double Resist Process, Joseph Jech Jr

Journal of the Microelectronic Engineering Conference

A hierarchical analysis of variance was executed on both critical dimension and film thickness data to prove manufacturability of a double layer resist process as compared to an existing device process. Testing was designed to provide estimates of variance on a die—to—die, wafer—to— wafer, and run-to—run basis. Ion implant mask sidewall angle and process repeatability were other concerns investigated. The double resist process displayed improvement in all phases of the process examined except the run—to— run variance of the polysilicon film thickness. More testing is required to determine if the possible cause was related to the process or some outside …

Fully Recessed Oxide Isolation Technology For Nmos Fabrication, Ronald G. Jones Jr

Journal of the Microelectronic Engineering Conference

Fully Recessed Oxide Isolation Technology (FROIT) and LOCOS methods were both fabricated to verify if the FROIT process provides solutions to two major problems associated with LOCOS, namely the bird’s beak formation and surface topography. The FROIT process uses a two step field oxidation and employs a nitride sidewall to recess the oxide and reduce the bird's beak, respectively. The SEM results verified the FROIT process achieved the desired results.

Alignment Error Characterization Using Electrical Probing Techniques, Jeffrey D. Kosa

Journal of the Microelectronic Engineering Conference

A technique for electrically measuring alignment errors is described and employed to characterize a GCA 4800 DSW stepper. The experimental accuracy was determined to be +I~ 0.05 microns for all line-width measurements. The GCA 4800 stepper’s day - to - day performance was determined to fluctuate between 0 and -1 micron in X and between 0 and +2 microns in Y. Average alignment ranges of +/- 0.74 and +/-0.95 microns in X and Y were ob served across four samples during the wafer-to-wafer variation testing within one run. These errors were directly related to the accuracy of the “pass-shift” values …

Evaluation Of Polyoxide Capacitor Edge Effects Using Ramped I-V Measurements, Loren C. Krott

Journal of the Microelectronic Engineering Conference

Thermally grown oxide on poly silicon has poorer insulator properties than an oxide grown on single crystal silicon. Due to surface roughness of the polysilicon surface the localized oxide electric field is enhanced at the surface bumps and asperities. In order to minimize surface roughness attention has to be given to the poly silicon surface for the steps following deposition. This includes doping and annealing the polysilicon in order to increase the grain size and using care in cleaning the poly and growing the oxide. By minimizing the surface roughness the poly oxide has better insulating properties due to a …

Fabrication Of T-Gate Structures Using Double Layer E-Beam Lithography, Eric A. Lehner

Journal of the Microelectronic Engineering Conference

The fabrication of T-gate structures using a bilayer resist scheme of PMMA 495K molecular weight (4% solids) and PMMA 950K molecular weight (3~ solids) for use with electron beam exposure was investigated. The 1.18 sensitivity ratio between these resists was found to be insufficient to adequately provide the resist cavity necessary for fabrication of T-gate aluminum structures.

Local Stress Field Determination For Thin Polysilicon Films, Pirouz Maghsoudnia

Journal of the Microelectronic Engineering Conference

Local stress field determination by means of free standing structures was investigated. The process for manufacturing these structures was developed and used to study the stress in polysilicon films.. For a 1.5um polysilicon film, the stress was determined to be less than 6.77e8Dynes/cm2. For a 0.5um polysilicon films, the stress was found to be 4. O9e8Dynes/cm2.

Fabrication Of Micromechanical Devices: Pin Joints, Sliders, Springs, And Micromotors, Matthew P. Matessa

Journal of the Microelectronic Engineering Conference

Movable pin Joints, springs, sliders and Rotors have been constructed using silicon fabrication technology. The movable mechanical elements are built using sacrificial layers that are later removed to allow translation and rotation of the structures [1]. The devices obtained physical movement and the rotors of the Rotors spun with compressed air, but electrical rotation of the motors was not accomplished.

Solar Cell Design Employing A Textured Surface, Diane M. Mauersberg

Journal of the Microelectronic Engineering Conference

Planar-junction, 1 mm x 1 mm, p+/n/n+ silicon solar cells, both with and without a textured surface, were fabricated in order to study the effects of decreased surface reflectance on cell efficiency. The texturing process was performed through the use of a KOH preferential etchant and an array of 10um x 10um windows to form an oxide masking layer. Inverted pyramids etched to points with final base widths being 13.7 microns due to undercutting of the masking oxide. Completed cells, evaluated at an irradiance of 100 mW/cm2, showed greater efficiences for the textured surface, but outputs of both were limited …

Determination Of Si02 Profiles Achievable With Rie Using C2f6 And Chf3, Daniel P. Morvay

Journal of the Microelectronic Engineering Conference

A dry etch S1O2 process was optimized using the Plasmatrac 2406 RIE etcher at RIT, while maintaining selectivity to polysilicon and photoresist. The optimized process had Power of 350 Watts, Pressure of 127 mTorr, C2F6 of 60 sccm, and CHF3 of 171 sccm; This provided an oxide to poly selectivity of 5.5:1 with an oxide slope of 60°.

Bicmos Vs Cmos At Rit, Anatole Raif

Journal of the Microelectronic Engineering Conference

This project involved the performance comparison of the standard RIT N-well CMOS and a proposed BiCMOS processes. Device parameters were extracted from TMA SUPREM-3 simulations and used to create NPN, PMOS, and NMOS model cards for ~ccusim simulations. Two inverter circuits, one in CMOS and one in BiCMOS were designed to drive a 5OpF load. The BiCMOS circuit was determined to be four times faster, less temperature dependent, and considerably smaller than its CMOS counterpart. These results lead to a final conclusion favoring the development and use of BiCMOS here at RIT.