Engineering Commons^™

Integration Of High-K Dielectrics And Metal Gates Into Submicron Nmos Transistors At Rit, Daniel J. Jaeger

Journal of the Microelectronic Engineering Conference

Zirconium oxide, a high-k gate dielectric, and molybdenum, a refractory metal, were successfully integrated into an existing submicron NMOS transistor process at RIT. Submicron high-k gate dielectric metal gate transistors were produced as a result of this project, and electrical characteristics were compared to reference submicron transistors fabricated with 75 A silicon dioxide gate dielectrics and polysilicon gates.

Nmos Transistors Design And Fabrication For S-Parameter Extraction, Adam L. James

Journal of the Microelectronic Engineering Conference

A successful test layout for S-parameter analysis was demonstrated. Process characterization accomplished as part of this project demonstrated a pseudo-shallow trench isolation. Active device measurements would have been possible with a DC blocking fixture. 0.37 μm-I.0 μm transistors were fabricated with a non-ideal characteristic which i~as due to the source drain implant being blocked by oxide residue from the spacer formation etch.

Esaki Tunnel Diodes Formed By Proximity Rapid Thermal Diffusion, Raymond T. Krom Iii

Journal of the Microelectronic Engineering Conference

For the first time tunnel diodes have been fabricated by Proximity Rapid Thermal Diffusion (PRTD) using spin on sources and the AG Associates 610 Rapid Thermal Annealing Furnace (RTA) at RIT. Initial devices revealed a maximum peak-to-valley current ratio (PVCR) of 1.3 with a peak current density (J_p) of l6mA/cm² at 300K. A second-generation design involving proximity diffusion of Boron and Phosphorous resulted in a higher J_p, of 3A/cm² and an elevated PVCR of 1.97 at 300K. The increased performance is attributed to closer matching of the doping profiles via the phosphorous proximity anneal. …

Field Induced Band-To-Band Tunneling Effect Transistor (Fibtet), David Pawlik

Journal of the Microelectronic Engineering Conference

A field Induced Band to Band Tunneling Effect Transistor was designed, fabricated and tested. The devices are to take the shape of finFETs and plainer devices i~hich will employ mesa isolation technology. Degenerate dopings were achieved through the use of proximity diffusion in a rapid thermal processing tool. Final results include design parameters, fabrication parameters, fabrication techniques, SEM Images, electrical test results & analysis, and areas of continuing work.

Printing Of Contact Holes For The 45nm Generation Using Immersion Interference Lithography, Michael A. Slocum

Journal of the Microelectronic Engineering Conference

Interference lithography is a valuable tool for evaluating photoresist performance at the resolutions unattainable with conventional exposure tools. interference lithography is most commonly used to generate one dimensional patterns such as lines and spaces. however two dimensional patterns are of much greater interest to both the resist developers and the device manufacturers in microlithography. This paper presents a technique to produce two dimensional images of contact holes at the resolution of 45nm half pitch. To our knowledge this is the highest resolution contacts printed to date using 193nm radiation. Photoresist patterns with a half-pitch of 45 nm were formed with …

In-Situ Aberration Metrology Using Phase Wheel Targets, Matthew M. Mcquillan

Journal of the Microelectronic Engineering Conference

Aberration metrology and monitoring of lithography projection systems in the semiconductor industry are becoming more important as today’s ICs are printed at sub-100 nm resolution. All lenses suffer from lens aberrations and it is important that the lithographer knows which aberration and the magnitude of the aberration in order to understand its impact on the process window and resolution limitations. A technique and process to recognize and measure lens aberrations in-situ has been developed using a phase wheel target at 157nm and 193nm lithography. This project will use the phase wheel target technique to extend aberration monitoring into i-line lithography …

Characterization And Optimization Of A Bi-Layer Barc, Ryan M. Stamp

Journal of the Microelectronic Engineering Conference

Standing wave effects have been seen throughout the history of microlithography. Due to standing wave effects, the line width control of imaged lines in photoresist is compromised. A technology that has emerged as strong solution for the reduction of standing wave effects is a Bottom Antireflective Coating (BARC) that is deposited onto the wafer before the photoresist deposition. By reducing the substrate reflectivity, the standing wave effects can also be reduced dramatically.

The 193 nm photoresist and the bi-layer BARC films were characterized and then optimized to reduce standing wave effects within the 193 nm photoresist. A bi-layer BARC film …

Optical Modulation In Silicon And The Orpel Device, Robin A. Joyce

Journal of the Microelectronic Engineering Conference

Optical modulation is discussed and ORPEL, an optical modulation device in silicon, is presented. A paradigm for signal modulation is theorized and reflectance spectra are presented showing a “resonance” condition. In addition, an analysis of failures during device processing is given.

Electromigration Testing At Rit: Thermal Test Development, Lance W. Barron

Journal of the Microelectronic Engineering Conference

An electromigration (EM) test mask was designed to utilize both standard ASTM and Standard Wafer-level Electromigration Accelerated Test Structures (SWEAT) fourterminal EM test structures of varying line-widths. The mask was used to pattern 4” test wafers consisting of 300 nm of sputtered aluminum-1% silicon on a thermal SiO2 layer. A custom thermal setup was developed for a Micromanipulator 6000 manual probe station. A new 4” brass chuck was machined to include cooling channels, wafer vacuum, and a thermocouple monitoring system. A resistive ring heater was bonded to the chuck and was controlled via a process temperature controller. Extensive electrical test …

Characterization Of Low Temperature Gate Dielectrics For Thin Film Transistors, G Robert Mulfinger

Journal of the Microelectronic Engineering Conference

The goal of this investigation was to ascertain a viable low temperature gate dielectric for an emerging TFT fabrication process at RIT. Various candidates were investigated to find the best solution for a low temperature gate dielectric. Materials studied include low temperature oxide (LTO) using low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) silicon nitride, and PECVD Tetra Ethyl Ortho Silicate (TEOS). Capacitors were fabricated with these materials, as well as a standard thermal oxide as a control. Wafers were examined both with and without anneals at 600°C in order to study bulk oxide and interface …

Low Temperature Dopant Activation, Eric Woodard

Journal of the Microelectronic Engineering Conference

A major area of research for integrated electronic systems is the development of systems on glass or plastic to optimize the performance/cost tradeoff. These new substrate materials impose significant constraints on electronic device fabrication, including limitations on chemical and thermal processes. Processes that do not use high temperatures have the increased flexibility needed to be used on new substrate materials. Amorphous silicon thin-film transistors (TFTs) have been fabricated at temperatures below 300°C, where in-situ doped layers are deposited to form the electrode regions. Unfortunately, the electrical activation and carrier mobility in these devices is exceedingly low. The conventional method of …

Integration Of Nickel Monosilicide (Nisi) Into An Rit Smfl Nmos Device, Phu Do

Journal of the Microelectronic Engineering Conference

A nickel silicidation process has been developed for the Semiconductor & Microsystems Fabrication Laboratory (SM FL) at Rochester Institute of Technology (RIT). NISI and Ni₂Si were obtained in doped source/drain and polysilicon gate regions respectively at rapid thermal annealing (RTA) condition of 500°C for 60 seconds. The sheet resistance of nickel silicide in both regions was measured to be 0.45Ω/o — 0.5Ω/o. Nickel silicide was also integrated into an RIT NMOSFET process where silicide was formed over the S/D and polysilicon gate regions. Rutherford Backscatter and x-ray diffraction data showed the formation of NiSi phase in the S/D …

Characterization Of Tisi2 Process And Electrical Properties, Laurel E. Haydock

Journal of the Microelectronic Engineering Conference

The goal of this experimentation consists of the formation of TiSi₂ and demonstration of its electrical properties. The successful formation of a TiSiproduct was be confirmed by scanning electron micrograph (SEM) images, Rutherford Backscatter Spectroscopy (RBS) data, and electrical characterization. Following an annealing heat treatment, the RBS data indicated the presence of a Si substrate, a film that compositionally appears to be TiSi₂, and a surface layer of TiO₂. The electrical testing indicates the presence of ohmic behavior, and the resistance is strongly dependant on the furnace annealing and rapid thermal processing (RTP) treatments.

Design And Manufacturing Of Silicon Pin Diodes Utilizing Silicon On Insulator Technology, Patrick Warner

Journal of the Microelectronic Engineering Conference

The goal of this project was to design a process to form a PIN structure on silicon on insulator (SOl) wafers, IBIS donated the wafers for this project. Using a combination of standard and novel wafer processing techniques allowed for successful completion of the device. These techniques involved a four-layer mask process that utilized both state of the art and older tool sets. A methodology for lithographic processing of wafer pieces has been expanded upon and documented for future use.

Testing demonstrated resistor like behavior opposed to the expected diode behavior. This result is indicative of a short through the …

Implementation Of A J-Ramp Test Process To Examine The Reliability Of Dielectric Films, William Simpson

Journal of the Microelectronic Engineering Conference

As film thicknesses get smaller and smaller it is important to maintain high quality dielectric films. A J-ramp test is a method for extracting the characteristics of dielectric films breakdown. Two important parameters that can be extracted using a i-ramp test are the maximum electric field and the charge to breakdown (QBD) of the dielectric. The charge to breakdown the dielectric is a very important parameter because it will be significantly affected by moderate changes within a dielectric. Historically, this parameter would be obtained through stress tests, using a single current level measurement that may take hours or even days. …

Development Of A Polysilicon Check Microvalve, William C. Hart

Journal of the Microelectronic Engineering Conference

Check valves are used frequently within the field of microfluidic MEMS, particularly in micropump applications. Check valves serve to limit the flow of a fluid to one direction through a channel. This project was an attempt to manufacture an efficient check microvalve using polysilicon as the valve cover material. Previous work on a microvalve at RIT has been unsuccessful, as the final KOH etch has attacked the polysilicon, thus removing the valves from the openings in the silicon. It was determined that pinholes in the LPCVD nitride were allowing KOH to penetrate the etch mask and attack the substrate surface …

Development Of Macroporous Silicon For Bio-Chemical Sensing Applications, Tiffany M. Hoover

Journal of the Microelectronic Engineering Conference

Macroporous silicon bio-chemical sensing devices have been developed, fabricated and tested. The porous silicon walls were lined with oxide and aluminum electrodes were placed on either side of the porous silicon membrane. These electrodes were used to measure capacitive changes resulting from vapor/fluidic interactions with the oxide-coated porous silicon membrane.

For thick flow-through membrane formation, the maximum etch time investigated during the porous silicon-forming anodization process, using an electrolyte consisting of hydrofluoric acid and dimethylformamide was an 8 hour period with an electrolyte refresh halfway through the process. The pore dimensions measured after this process were approximately 67 μm …

Mems Based Light Modulator, Shushil Shakya

Journal of the Microelectronic Engineering Conference

This paper presents a simple way to build a MEMS based light modulator. Here Aluminum ribbons are suspended in an air gap. An array of these Al ribbons can be used to act as a light modulator. Alternate Al ribbons are connected to a DC bias of 50V which will curve downwards due to the stress applied and electrostatic attraction. Thus, the light intensity can be modulated to any shade of gray needed or even turn it off completely. Different sizes of light modulators were built using Mentor Graphics and were fabricated in the RIT, SMFL. Final results did not …