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8 Bit Split Array Based Charge Scaling Digital To Analog Converter With Rail To Rail Buffered Output, Sai Kiran Akula
8 Bit Split Array Based Charge Scaling Digital To Analog Converter With Rail To Rail Buffered Output, Sai Kiran Akula
Graduate Theses and Dissertations
This thesis presents the design, simulation and layout of a silicon carbide (SiC) 8 bit split array charge scaling digital to analog convertor (DAC). The converter consists of the charge scaling capacitor chain with two operational trans-conductance amplifiers (op amp) in voltage follower configuration. The op amps used in the design have the input common mode ranges of 0 to 11.2 V and 4.7V to 14.5V respectively. Additional logic circuit topologies are designed, which help to switch the op amps when needed to provide a rail to rail unity gain at the output. As the design is based on the …