Engineering Commons^™

Assuring Netlist-To-Bitstream Equivalence Using Physical Netlist Generation And Structural Comparison, Reilly Mckendrick, Jeffrey Goeders, Keenan Faulkner

Faculty Publications

Hardware netlists are generally converted into a bitstream and loaded onto an FPGA board through vendor-provided tools. Due to the proprietary nature of these tools, it is up to the designer to trust the validity of the design’s conversion to bitstream. However, motivated attackers may alter the CAD tools’ integrity or manipulate the stored bitstream with the intent to disrupt the functionality of the design. This paper proposes a new method to prove functional equivalence between a synthesized netlist, and the produced FPGA bitstream. The novel approach is comprised of two phases: first, we show how we can utilize implementation …

A Design Strategy To Improve Machine Learning Resiliency Of Physically Unclonable Functions Using Modulus Process, Yuqiu Jiang

Theses and Dissertations

Physically unclonable functions (PUFs) are hardware security primitives that utilize non-reproducible manufacturing variations to provide device-specific challenge-response pairs (CRPs). Such primitives are desirable for applications such as communication and intellectual property protection. PUFs have been gaining considerable interest from both the academic and industrial communities because of their simplicity and stability. However, many recent studies have exposed PUFs to machine-learning (ML) modeling attacks. To improve the resilience of a system to general ML attacks instead of a specific ML technique, a common solution is to improve the complexity of the system. Structures, such as XOR-PUFs, can significantly increase the nonlinearity …

Qasm-To-Hls: A Framework For Accelerating Quantum Circuit Emulation On High-Performance Reconfigurable Computers, Anshul Maurya

Theses and Dissertations

High-performance reconfigurable computers (HPRCs) make use of Field-Programmable Gate Arrays (FPGAs) for efficient emulation of quantum algorithms. Generally, algorithm-specific architectures are implemented on the FPGAs and there is very little flexibility. Moreover, mapping a quantum algorithm onto its equivalent FPGA emulation architecture is challenging. In this work, we present an automation framework for converting quantum circuits to their equivalent FPGA emulation architectures. The framework processes quantum circuits represented in Quantum Assembly Language (QASM) and derives high-level descriptions of the hardware emulation architectures for High-Level Synthesis (HLS) on HPRCs. The framework generates the code for a heterogeneous architecture consisting of a …

Accelerating Machine Learning Inference For Satellite Component Feature Extraction Using Fpgas., Andrew Ekblad

Theses and Dissertations

Running computer vision algorithms requires complex devices with lots of computing power, these types of devices are not well suited for space deployment. The harsh radiation environment and limited power budgets have hindered the ability of running advanced computer vision algorithms in space. This problem makes running an on-orbit servicing detection algorithm very difficult. This work proposes using a low powered FPGA to accelerate the computer vision algorithms that enable satellite component feature extraction. This work uses AMD/Xilinx’s Zynq SoC and DPU IP to run model inference. Experiments in this work centered around improving model post processing by creating implementations …

Normalized Linearly-Combined Chaotic System: Design, Analysis, Implementation And Application, Md Sakib Hasan, Anurag Dhungel, Partha Sarathi Paul, Maisha Sadia, Md Razuan Hossain

Faculty and Student Publications

This work presents a general framework for developing a multi-parameter 1-D chaotic system for uniform and robust chaotic operation across the parameter space. This is important for diverse practical applications where parameter disturbance may cause degradation or even complete disappearance of chaotic properties. The wide uninterrupted chaotic range and improved chaotic properties are demonstrated with the aid of stability analysis, bifurcation diagram, Lyapunov exponent (LE), Kolmogorov entropy, Shannon entropy, and correlation coefficient. We also demonstrate the proposed system’s amenability to cascading for further performance improvement. We introduce an efficient Field-Programmable Gate Array (FPGA)-based implementation and validate its chaotic properties using …

Development Of The Digital Signal Processing For The Space Weather Probes Version 2 Sensor Using The Matlab/Simulink Environment, Benjamin J. Lewis

All Graduate Theses and Dissertations, Spring 1920 to Summer 2023

Space Weather Probes (SWP) is an instrument that provides measurements of the plasma environment of the ionosphere. SWP was flown on the Scintillation Prediction Observation Task (SPORT) mission, a joint mission between the United States of America and Brazil. This thesis will develop the digital signal processing (DSP) hardware design for the Space Weather Probes version 2 (SWP2). The data from these instruments will be used to determine the density and temperature of the local plasma, as well as the electric field in the local plasma. This thesis presents the design and testing of the DSP designs for all of …

A Reconfigurable Architecture For Matrix Multiplication For Low Power Applications, Jeffrey Love

Electrical and Computer Engineering ETDs

This thesis presents a hardware architecture for performing matrix multiplication via a systolic array to reduce time complexity and power consumption. The proposed architecture, the Neural Network Accelerator (NNA), was designed in Verilog HDL to perform 8-bit multiplication to reduce the resources required to implement the NNA on low-power FPGAs. The NNA’s open architecture is designed to support radiation test for fault tolerant designs targeting space applications. Commercial hardware architecture information is not public knowledge, which led us to build our own matrix multiplication architecture so that we could later study its feasibility for space applications.

The NNA was compared …

Approximate Computing Based Processing Of Mea Signals On Fpga, Mohammad Emad Hassan

Dissertations

The Microelectrode Array (MEA) is a collection of parallel electrodes that may measure the extracellular potential of nearby neurons. It is a crucial tool in neuroscience for researching the structure, operation, and behavior of neural networks. Using sophisticated signal processing techniques and architectural templates, the task of processing and evaluating the data streams obtained from MEAs is a computationally demanding one that needs time and parallel processing.

This thesis proposes enhancing the capability of MEA signal processing systems by using approximate computing-based algorithms. These algorithms can be implemented in systems that process parallel MEA channels using the Field Programmable Gate …