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Articles 1 - 6 of 6
Full-Text Articles in Engineering
Linear Current-Mode Active Pixel Sensor, Ralf M. Philipp, David Orr, Viktor Gruev, Jan Van Der Spiegel, Ralph Etienne-Cummings
Linear Current-Mode Active Pixel Sensor, Ralf M. Philipp, David Orr, Viktor Gruev, Jan Van Der Spiegel, Ralph Etienne-Cummings
Jan Van der Spiegel
A current mode CMOS active pixel sensor (APS) providing linear light-to-current conversion with inherently low fixed pattern noise (FPN) is presented. The pixel features adjustable-gain current output using a pMOS readout transistor in the linear region of operation. This paper discusses the pixel’s design and operation, and presents an analysis of the pixel’s temporal noise and FPN. Results for zero and first-order pixel mismatch are presented. The pixel was implemented in a both a 3.3 V 0.35 µm and a 1.8 V 0.18 µm CMOS process. The 0.35 µm process pixel had an uncorrected FPN of 1.4%/0.7% with/without column readout …
A Fully Integrated Cmos Phase-Locked Loop With 30mhz To 2ghz Locking Range And ±35 Ps Jitter, Chao Xu, Winslow Sargeant, Kenneth R. Laker, Jan Van Der Spiegel
A Fully Integrated Cmos Phase-Locked Loop With 30mhz To 2ghz Locking Range And ±35 Ps Jitter, Chao Xu, Winslow Sargeant, Kenneth R. Laker, Jan Van Der Spiegel
Jan Van der Spiegel
A fully integrated phase-locked loop (PLL) fabricated in a 0.24μm, 2.5v digital CMOS technology is described. The PLL is intended for use in multi-gigabit-per-second clock recovery circuits in fiber-optic communication chips. This PLL first time achieved a very large locking range measured to be from 30MHz up to 2GHz in 0.24μm CMOS technologies. Also it has very low peak-to-peak jitter less than ±35ps at 1.25GHz output frequency.
Analytical And Experimental Studies Of Thermal Noise In Mosfet's, Suharli Tedja, Jan Van Der Spiegel, Hugh H. Williams
Analytical And Experimental Studies Of Thermal Noise In Mosfet's, Suharli Tedja, Jan Van Der Spiegel, Hugh H. Williams
Jan Van der Spiegel
An analysis of the channel thermal noise in MOSFET's, based on the one-dimensional charge sheet model, is presented. The analytical expression is valid in the strong, moderate, and weak inversion regions. The body effect on the device parameters relevant to the thermal noise is discussed. A measurement technique as well as experimental results of P- and N-MOSFET's of a 1.2 µm radiation hard CMOS process are presented. The calculated channel thermal noise coefficient gamma as in id2/Δf=4kT γ gdo agrees well with experimental data for effective device channel length as short as 1.7µm.
Background Digital Error Correction Technique For Pipelined Analog-Digital Converters, Sameer R. Sonkusale, Jan Van Der Spiegel, K. Nagaraj
Background Digital Error Correction Technique For Pipelined Analog-Digital Converters, Sameer R. Sonkusale, Jan Van Der Spiegel, K. Nagaraj
Jan Van der Spiegel
This paper describes a technique for digital error correction in pipelined analog-digital converters. It makes use of a slow, high resolution ADC in conjunction with an LMS algorithm to perform error correction in the background during normal conversion. The algorithm will be shown to correct for errors due to capacitor ratio mismatch, finite amplifier gain and charge injection within the same framework.
Fully Integrated Cmos Phase-Locked Loop With 30mhz To 2ghz Locking Range And +-35ps Jitter, Chao Xu, Winslow Sargeant, Kenneth R. Laker, Jan Van Der Spiegel
Fully Integrated Cmos Phase-Locked Loop With 30mhz To 2ghz Locking Range And +-35ps Jitter, Chao Xu, Winslow Sargeant, Kenneth R. Laker, Jan Van Der Spiegel
Jan Van der Spiegel
A fully integrated phase-locked loop (PLL) fabricated in a 0.24 micrometer, 2.5v digital CMOS technology is described. The PLL is intended for use in multi-gigabit-per-second clock recovery circuits in fiber-optic communication chip. This PLL first time achieved a very large locking range measured to be from 30MHz up to 2GHz in 0.24 micrometer CMOS technology. Also it has very low peak-to-peak jitter less than +-35ps at 1.25GHz output frequency.
Gbopcad: A Synthesis Tool For High-Performance Gain-Boosted Opamp Design, Jie Yuan, Nabil H. Farhat, Jan Van Der Spiegel
Gbopcad: A Synthesis Tool For High-Performance Gain-Boosted Opamp Design, Jie Yuan, Nabil H. Farhat, Jan Van Der Spiegel
Jan Van der Spiegel
A systematic design methodology for high-performance gain-boosted opamps (GBOs) is presented. The methodology allows the optimization of the GBO in terms of ac response and settling performance and is incorporated into an automatic computer-aided design (CAD) tool, called GBOPCAD. Analytic equations and heuristics are first used by GBOPCAD to obtain a sizing solution close to the global optimum. Then, simulated annealings are used by GBOPCAD to find the global optimum. A sample opamp is designed by this tool in a 0.6-μm CMOS process. It achieves a dc gain of 80 dB, a unity-gain bandwidth of 836 MHz with 60o phase …