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Electrical and Computer Engineering

Faculty Publications

Annealing

Articles 1 - 5 of 5

Full-Text Articles in Engineering

Effect Of Fabrication Parameters On The Ferroelectricity Of Hafnium Zirconium Oxide Films: A Statistical Study, Guillermo A. Salcedo, Ahmad E. Islam, Elizabeth Reichley, Michael Dietz, Christine M. Schubert Kabban, Kevin D. Leedy, Tyson C. Back, Weison Wang, Andrew Green, Timothy S. Wolfe, James M. Sattler Mar 2024

Effect Of Fabrication Parameters On The Ferroelectricity Of Hafnium Zirconium Oxide Films: A Statistical Study, Guillermo A. Salcedo, Ahmad E. Islam, Elizabeth Reichley, Michael Dietz, Christine M. Schubert Kabban, Kevin D. Leedy, Tyson C. Back, Weison Wang, Andrew Green, Timothy S. Wolfe, James M. Sattler

Faculty Publications

Ferroelectricity in hafnium zirconium oxide (Hf1−xZrxO2) and the factors that impact it have been a popular research topic since its discovery in 2011. Although the general trends are known, the interactions between fabrication parameters and their effect on the ferroelectricity of Hf1−xZrxO2 require further investigation. In this paper, we present a statistical study and a model that relates Zr concentration (x), film thickness (tf), and annealing temperature (Ta) with the remanent polarization (Pr) in tungsten (W)-capped Hf1−xZrxO2. …


Iii-Nitride Transistors With Capacitively Coupled Contacts, Grigory Simin, Z.-J. Yang, A. Koudymov, V. Adivarahan, M. Asif Khan Jul 2006

Iii-Nitride Transistors With Capacitively Coupled Contacts, Grigory Simin, Z.-J. Yang, A. Koudymov, V. Adivarahan, M. Asif Khan

Faculty Publications

AlGaN∕GaNheterostructure field-effect transistor design using capacitively coupled contacts (C3HFET) is presented. Insulated-gate [C3 metal-oxide-semiconductor HFET(C3MOSHFET)] has also been realized. The capacitively coupled source, gate, and drain of C3 device do not require annealedOhmic contacts and can be fabricated using gate alignment-free technology. For typical AlGaN∕GaNheterostructures, the equivalent contact resistance of C3 transistors is below 0.6Ωmm. In rf-control applications, the C3HFET and especially the C3MOSHFET have much higher operating rf powers as compared to HFETs.C3 design is instrumental for studying the two-dimensional electron gas transport in other wide band gap …


Very-Low-Specific-Resistance Pd/Ag/Au/Ti/Au Alloyed Ohmic Contact To P Gan For High-Current Devices, V. Adivarahan, A. Lunev, M. Asif Khan, J. Yang, Grigory Simin, M. S. Shur, R. Gaska Apr 2001

Very-Low-Specific-Resistance Pd/Ag/Au/Ti/Au Alloyed Ohmic Contact To P Gan For High-Current Devices, V. Adivarahan, A. Lunev, M. Asif Khan, J. Yang, Grigory Simin, M. S. Shur, R. Gaska

Faculty Publications

We report on Pd/Ag/Au/Ti/Au alloyed metallic contact to pGaN. An 800 °C anneal for 1 min in flowing nitrogen ambient produces an excellent ohmic contact with a specific contact resistivity close to 1×10−6 Ω cm2 and with good stability under high current operation conditions. This high-temperature anneal forms an alloy between Ag,Au, and pGaN resulting in a highly p-doped region at the interface. Using x-ray photoelectron spectroscopy and x-ray diffractionanalysis, we confirm that the contact formation mechanism is the metal intermixing and alloying with the semiconductor.


Low-Frequency Noise In 4h-Silicon Carbide Junction Field Effect Transistors, J. W. Palmour, M. E. Levinshtein, S. L. Rumyantsev, Grigory Simin May 1996

Low-Frequency Noise In 4h-Silicon Carbide Junction Field Effect Transistors, J. W. Palmour, M. E. Levinshtein, S. L. Rumyantsev, Grigory Simin

Faculty Publications

Low frequency noise in 4H‐silicon carbide junction field effect transistors (JFETs) has been investigated. JFETs with a buried p + n junction gate were manufactured by CREE Research Inc. Very low noise level has been observed in the JFETs. At 300 K the value of Hooge constant α is as small as α∼10−5 and the α value can be decreased by an appropriate annealing to α∼2×10−6. It has been shown that even these extremely low noise values are determined not by the volume noise sources but by the noise at the SiC–SiO2 interface.


Low‐Cost Technique For Preparing N‐Sb2S3/P‐Si Heterojunction Solar Cells, O. Savadogo, K. C. Mandal Jul 1993

Low‐Cost Technique For Preparing N‐Sb2S3/P‐Si Heterojunction Solar Cells, O. Savadogo, K. C. Mandal

Faculty Publications

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