Engineering Commons^™

H.264 Video Decoder Implemented On Fpgas Using 3×3 And 2×2 Networks-On-Chip, Ian Barge, Cristinel Ababei

Electrical and Computer Engineering Faculty Research and Publications

In this paper, we present the design and verification of the H.264 video decoder algorithm on FPGAs. The primary difference compared to previously reported designs is that the communication between the decoder modules is done via a network-on-chip in our case. The proposed design is a complete system level hardware design described in VHDL and Verilog. We report experimental results for two different implementations. The first implementation uses a 3×3 network-on-chip and is validated on the DE4 development board, which uses Altera's Stratix IV GX FPGA chip. The second implementation uses a 2×2 network-on-chip and is validated on the Cyclone …