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H.264 Video Decoder Implemented On Fpgas Using 3×3 And 2×2 Networks-On-Chip, Ian Barge, Cristinel Ababei
H.264 Video Decoder Implemented On Fpgas Using 3×3 And 2×2 Networks-On-Chip, Ian Barge, Cristinel Ababei
Electrical and Computer Engineering Faculty Research and Publications
In this paper, we present the design and verification of the H.264 video decoder algorithm on FPGAs. The primary difference compared to previously reported designs is that the communication between the decoder modules is done via a network-on-chip in our case. The proposed design is a complete system level hardware design described in VHDL and Verilog. We report experimental results for two different implementations. The first implementation uses a 3×3 network-on-chip and is validated on the DE4 development board, which uses Altera's Stratix IV GX FPGA chip. The second implementation uses a 2×2 network-on-chip and is validated on the Cyclone …
An Efficient And Cost Effective Fpga Based Implementation Of The Viola-Jones Face Detection Algorithm, Peter Irgens, Curtis Bader, Theresa Lé, Devansh Saxena, Cristinel Ababei
An Efficient And Cost Effective Fpga Based Implementation Of The Viola-Jones Face Detection Algorithm, Peter Irgens, Curtis Bader, Theresa Lé, Devansh Saxena, Cristinel Ababei
Electrical and Computer Engineering Faculty Research and Publications
We present an field programmable gate arrays (FPGA) based implementation of the popular Viola-Jones face detection algorithm, which is an essential building block in many applications such as video surveillance and tracking. Our implementation is a complete system level hardware design described in a hardware description language and validated on the affordable DE2-115 evaluation board. Our primary objective is to study the achievable performance with a low-end FPGA chip based implementation. In addition, we release to the public domain the entire project. We hope that this will enable other researchers to easily replicate and compare their results to ours and …