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Modeling Multilayered Pcb Power-Bus Designs Using An Mpie Based Circuit Extraction Technique, Hao Shi, Jun Fan, James L. Drewniak, Todd H. Hubing, Thomas Van Doren
Modeling Multilayered Pcb Power-Bus Designs Using An Mpie Based Circuit Extraction Technique, Hao Shi, Jun Fan, James L. Drewniak, Todd H. Hubing, Thomas Van Doren
Electrical and Computer Engineering Faculty Research & Creative Works
A circuit extraction tool (CEMPIE) has been developed based on the mixed-potential integral equation (MPIE) using a quasi-static approximation. A power-bus in a multi-layered PCB consisting of a pair of dedicated ground and power planes is studied using this tool. The distributed behavior of a power-bus is represented by a collection of passive circuit elements, which is valid up to several gigahertz. The decoupling performance of a power-bus due to its layer spacing and the dielectric constant is evaluated for simple test geometries. The impact of the relative distance between the noise source and the potential receiver is also studied. …
Simulation And Measurement For Decoupling On Multilayer Pcb Dc Power Buses, Hao Shi, F. Yuan, Fei Sha, James L. Drewniak, Todd H. Hubing, Thomas Van Doren
Simulation And Measurement For Decoupling On Multilayer Pcb Dc Power Buses, Hao Shi, F. Yuan, Fei Sha, James L. Drewniak, Todd H. Hubing, Thomas Van Doren
Electrical and Computer Engineering Faculty Research & Creative Works
DC power bus decoupling of a multi-layer PCB is modeled by a combination of a lumped circuit model at low frequencies ( < 200 MHz), and a mixed-potential integral equation approach at high frequencies. In order to determine the lumped parameters of via interconnects, an effective procedure using a network analyzer has been developed to characterize the trace/via inductances/resistances. For an 8 inch × 10 inch ten-layer test board used in this study, the simulations show good agreement with the measurement. This method can lead to new design strategies of decoupling for multilayer PCB power buses.