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Analysis Of Dynamic Logic Circuits In Deep Submicron Cmos Technologies, Rahul C. Muppasani
Analysis Of Dynamic Logic Circuits In Deep Submicron Cmos Technologies, Rahul C. Muppasani
Electrical Engineering Theses
Dynamic logic circuits are utilized to minimize the delay in the critical path of high-performance designs such as the datapath circuits in state-of-the-art microprocessors. However, as integrated circuits (ICs) scale to the very deep submicron (VDSM) regime, dynamic logic becomes susceptible to a variety of failure modes due to decreasing noise margins and increasing leakage currents. The objective of this thesis is to characterize the performance of dynamic logic circuits in VDSM technologies and to evaluate various design strategies to mitigate the effects of leakage currents and small noise margins.
Optimization Of Short-Channel Rf Cmos Low Noise Amplifiers By Geometric Programming, Xiaoyu Jin
Optimization Of Short-Channel Rf Cmos Low Noise Amplifiers By Geometric Programming, Xiaoyu Jin
Electrical Engineering Theses
Geometric programming (GP) is an optimization method to produce globally optimal circuit parameters with high computational efficiency. Such a method has been applied to short-channel (90 nm and 180 nm) CMOS Low Noise Amplifiers (LNAs) with common-source inductive degeneration to obtain optimal design parameters by minimizing the noise figure. An extensive survey of analytical models and experimental results reported in the literature was carried out to quantify the issue of excessive thermal noise for short-channel MOSFETs. Geometric programming compatible functions have been determined to calculate the noise figure of short-channel CMOS devices by taking into consideration channel-length modulation and velocity …
An Evaluation Of Cmos Adders For Robustness And Fault Detectability In Nanoscale Technologies, Sowjanya Puttagunta
An Evaluation Of Cmos Adders For Robustness And Fault Detectability In Nanoscale Technologies, Sowjanya Puttagunta
Electrical Engineering Theses
The objective of this thesis is to implement the two low transistor count full adders using submicron CMOS technologies and to study their performance with respect to process variations and single-transistor faults. One adder uses 10 transistors and the other uses 14 transistors. Hence they are respectively called the 10T and 14T adders. Previous work has studied the implementation of the static Complementary Metal Oxide Semiconductor (CMOS) adder, Complementary Pass Transistor Logic (CPL) adder, Transmission Gate adder (TGA) and the Hybrid CMOS (HCMOS) adder. The performance of the 10T and 14 T adders using the above mentioned metrics are compared …