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Library and Information Science Commons

Open Access. Powered by Scholars. Published by Universities.®

Electrical and Computer Engineering

2020

Bus interconnection

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Full-Text Articles in Library and Information Science

Bibliometric Review Of Noc Router Optimization, Priti Shahane, Jayshree Pande Jan 2020

Bibliometric Review Of Noc Router Optimization, Priti Shahane, Jayshree Pande

Library Philosophy and Practice (e-journal)

Network on chip (NoC) has been proposed as an emerging solution for scalability and performance demands of next generation System on Chip (SoC). NoC provides a solution for the bus based interconnection issue of SoC, where large numbers of Intellectual Property modules (IP) are integrated on a single chip for better performance. The NoC has several advantages such as scalability, low latency and low power consumption, high bandwidth over dedicated wires and buses. Interconnections between multiple chip cores have a significant impact on the communication and performance of the chip design in terms of region, latency, throughput and power. In …