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Full-Text Articles in Physics

Exploring Gated Nanoelectronic Devices Fabricated From 1d And 2d Materials, Prathamesh A. Dhakras Jan 2019

Exploring Gated Nanoelectronic Devices Fabricated From 1d And 2d Materials, Prathamesh A. Dhakras

Legacy Theses & Dissertations (2009 - 2024)

One and two dimensional materials are being extensively researched toward potential application as ultra-thin body channel materials. The difficulty of implementing physical doping methods in these materials has necessitated various alternative doping schemes, the most promising of which is the electrostatic gating technique due to its reconfigurability. This dissertation explores the different fundamental devices that can be fabricated and characterized by taking advantage of the electrostatic gating of individual single-walled carbon nanotubes (SWNTs), dense SWNT networks and exfoliated 2D tungsten diselenide (WSe2) flakes.


Radiation Effects In Tantalum Oxide-Based Resistive Memory Devices, Joshua Stuart Holt Jan 2018

Radiation Effects In Tantalum Oxide-Based Resistive Memory Devices, Joshua Stuart Holt

Legacy Theses & Dissertations (2009 - 2024)

There is an increasing need for radiation-hardened electronics as space programs grow in number and scope. Scientific interest in long-term exploration, particularly in high-radiation environments such as Europa, as well as commercial interest in establishing permanent outposts, requires high tolerance of radiation effects. A flash memory device might survive for several years in low Earth orbit, but only a few days in orbit around Europa due to the extremely high levels of radiation encountered there. Meanwhile, commercial interests, including asteroid mining and building a base on the moon or Mars would require electronic systems that could survive for long periods …


Development Of Iii-Sb Based Technologies For P-Channel Mosfet In Cmos Applications, Shailesh Kumar Madisetti Jan 2016

Development Of Iii-Sb Based Technologies For P-Channel Mosfet In Cmos Applications, Shailesh Kumar Madisetti

Legacy Theses & Dissertations (2009 - 2024)

The continuous scaling of silicon CMOS predicts the end of roadmap due to the difficulties such as that arise from electrostatic integrity, design complexities, and power dissipation. These fundamental and practical limitations bring the need for innovative design architectures or alternate materials with higher carrier transport than current Si based materials. New device designs such as multigate/gate-all-around architectures improve electrostatics while alternate materials like III-Vs such as III-As for electrons and III-Sbs for holes increase operational speed, lower power dissipation and thereby improve performance of the transistors due to their low effective mass and faster transport properties. Further, application of …


Novel Two-Dimensional Devices For Future Applications, Pratik Agnihotri Jan 2016

Novel Two-Dimensional Devices For Future Applications, Pratik Agnihotri

Legacy Theses & Dissertations (2009 - 2024)

The scalability of field effect transistor has led to the monumental success of complementary metal-oxide-semiconductor (CMOS) technology. In the past, device scaling was not the major issue to a greater extent. Recently with current technology nodes, transistor characteristics show signs of reduced performance due to short channel effects and other issues related to device scaling. Device designers look for innovative ways to enhance the transistor performance while keeping up with device miniaturization. Successful inventions include the development of tri-gate technology, gate all around (GAA) field effect transistors, silicon-on-insulator substrate, and high-k dielectrics. These developments have enabled the device scaling that …


Extraction Of Carrier Mobility And Interface Trap Density In Ingaas Metal Oxide Semiconductor Structures Using Gated Hall Method, Thenappan Chidambaram Jan 2015

Extraction Of Carrier Mobility And Interface Trap Density In Ingaas Metal Oxide Semiconductor Structures Using Gated Hall Method, Thenappan Chidambaram

Legacy Theses & Dissertations (2009 - 2024)

III-V semiconductors are potential candidates to replace Si as a channel material in next generation CMOS integrated circuits owing to their superior carrier mobilities. Low density of states (DOS) and typically high interface and border trap densities (Dit) in high mobility group III-V semiconductors provide difficulties in quantification of Dit near the conduction band edge. The trap response above the threshold voltage of a MOSFET can be very fast, and conventional Dit extraction methods, based on capacitance/conductance response (CV methods) of MOS capacitors at frequencies <1MHz, cannot distinguish conducting and trapped carriers. In addition, the CV methods have to deal with high dispersion in the accumulation region that makes it a difficult task to measure the true oxide capacitance, Cox value. Another implication of these properties of III-V interfaces is an ambiguity of determination of electron density in the MOSFET channel. Traditional evaluation of carrier density by integration of the C-V curve, gives incorrect values for Dit and mobility. Here we employ gated Hall method to quantify the Dit spectrum at the high-κ oxide/III-V semiconductor interface for buried and surface channel devices using Hall measurement and capacitance-voltage data. Determination of electron density directly from Hall measurements allows for obtaining true mobility values


Electron Beam Lithography Throughput And Resolution Enhancement With Innovative Blanker Design, Junru Ruan Jan 2010

Electron Beam Lithography Throughput And Resolution Enhancement With Innovative Blanker Design, Junru Ruan

Legacy Theses & Dissertations (2009 - 2024)

Electron Beam Lithography (EBL) is one of the most important and most widely used methods for nano-fabrication. The primary advantage of electron beam lithography is its high resolution, and its ability to expose nanometer features without a mask. On the other hand, one of the key limitations of electron beam lithography is throughput. Slow blanking speed is one of the major bottlenecks for the system speed. In this dissertation, I will first review the prior literature of high speed blanking. Thorough theoretical and experimental studies are done on the existing designs. Physical models are built and analytical ray tracing is …