Nanoscience and Nanotechnology Commons^™

Toward Surround Gates On Vertical Single-Walled Carbon Nanotube Devices, Aaron D. Franklin, Robert A. Sayer, Timothy D. Sands, Timothy S. Fisher, David B. Janes

Robert A Sayer

The one-dimensional, cylindrical nature of single-walled carbon nanotubes (SWCNTs) suggests that the ideal gating geometry for nanotube field-effect transistors (FETs) is a surround gate (SG). Using vertical SWCNTs templated in porous anodic alumina, SGs are formed using top-down processes for the dielectric/metal depositions and definition of the channel length. Surround gates allow aggressive scaling of the channel to 25% of the length attainable with a bottom-gate geometry without incurring short-channel effects. The process demonstrated here for forming SGs on vertical SWCNTs is amenable for large-scale fabrication of multinanotube FETs.

Non-Silicon Mosfets And Circuits With Atomic Layer Deposited Higher-K Dielectrics, Lin Dong

Open Access Dissertations

The quest for technologies beyond 14nm node complementary metal-oxide-semiconductor (CMOS) devices has now called for research on higher-k gate dielectrics integration with high mobility channel materials such as III-V semiconductors and germanium. Ternary oxides, such as La2-xYxO3 and LaAlO3, have been considered as strong candidates due to their high dielectric constants and good thermal stability. Meanwhile, the unique abilities of delivering large area uniform thin film, excellent controlling of composition and thickness to an atomic level, which are keys to ultra-scaled devices, have made atomic layer deposition (ALD) technique an excellent choice.

In this thesis, we systematically study the atomic …