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AC conductance technique; interface states; interface traps; silicon carbide (SiC); wide-bandgap semiconductor
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Full-Text Articles in Nanoscience and Nanotechnology
Limitations Of The High-Low C-V Technique For Mos Interfaces With Large Time Constant Dispersion, Ashish Verma Penumatcha, Steven Swandono, James A. Cooper
Limitations Of The High-Low C-V Technique For Mos Interfaces With Large Time Constant Dispersion, Ashish Verma Penumatcha, Steven Swandono, James A. Cooper
Birck and NCN Publications
We discuss the limitations of the high-low CV technique in evaluating the interface trap density (D-TT) in MOS samples with a large time constant dispersion, as occurs in silicon carbide (SiC). We show that the high-low technique can seriously underestimate D-IT for samples with large time constant dispersion, even if elevated temperatures are used to extend the range of validity.