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Effects Of Gate-Last And Gate-First Process On Deep Submicron Inversion-Mode Ingaas N-Channel Metal-Oxide-Semiconductor Field Effect Transistors, J. J. Gu, Y. Q. Wu, Peide D. Ye

Birck and NCN Publications

Recently, encouraging progress has been made on surface-channel inversion-mode In-rich InGaAs NMOSFETs with superior drive current, high transconductance and minuscule gate leakage, using atomic layer deposited (ALD) high-k dielectrics. Although gate-last process is favorable for high-k/III-V integration, high-speed logic devices require a self-aligned gate-first process for reducing the parasitic resistance and overlap capacitance. On the other hand, a gate-first process usually requires higher thermal budget and may degrade the III-V device performance. In this paper, we systematically investigate the thermal budget of gate-last and gate-first process for deep-submicron InGaAs MOSFETs. We conclude that the thermal instability of (NH(4))(2)S as the …