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Full-Text Articles in Nanoscience and Nanotechnology
Graphene-Based Interconnects : Electrical Performance And Reliability, Tianhua Yu
Graphene-Based Interconnects : Electrical Performance And Reliability, Tianhua Yu
Legacy Theses & Dissertations (2009 - 2024)
According to the ITRS Roadmap, on-chip interconnects wire width and current density will reach 22 nm and 5.8×106 A/cm2 in 2020, respectively. The electrical resistivity of Cu increases with scaled critical dimensions due to exacerbated carrier scattering at grain boundaries and interfaces, resulting in signal speed degradation. Electronmigration (EM)-related failure due to intensified current distribution posts extra limits to ultra-scaled systems. Innovative interconnect solutions are needed to tackle performance and scaling challenges.
Applying X-Ray Microscopy And Finite Element Modeling (Fem) To Identify The Mechanism Of Stress-Assisted Void Growth In Through Silicon Via (Tsv), Lay Wai Kong
Legacy Theses & Dissertations (2009 - 2024)
Fabricating through-silicon vias (TSVs) is challenging, especially for conformally filled TSVs, often hampered by the seam line and void inside the TSVs. Stress-assisted void growth in TSVs has been studied by finite element stress modeling and X-ray computed tomography (XCT). Because X-ray imaging does not require TSVs to be physically cross-sectioned, the same TSV can be imaged before and after annealing. Using 8 keV laboratory-based XCT, voids formed during copper electroplating are observed in as-deposited samples and void growth is observed at the void location after annealing. We hypothesize that the mechanism generating voids is hydrostatic stress-assisted void growth. Stresses …