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Articles 1 - 10 of 10
Full-Text Articles in Nanoscience and Nanotechnology
Exploring Gated Nanoelectronic Devices Fabricated From 1d And 2d Materials, Prathamesh A. Dhakras
Exploring Gated Nanoelectronic Devices Fabricated From 1d And 2d Materials, Prathamesh A. Dhakras
Legacy Theses & Dissertations (2009 - 2024)
One and two dimensional materials are being extensively researched toward potential application as ultra-thin body channel materials. The difficulty of implementing physical doping methods in these materials has necessitated various alternative doping schemes, the most promising of which is the electrostatic gating technique due to its reconfigurability. This dissertation explores the different fundamental devices that can be fabricated and characterized by taking advantage of the electrostatic gating of individual single-walled carbon nanotubes (SWNTs), dense SWNT networks and exfoliated 2D tungsten diselenide (WSe2) flakes.
Extraction Of Carrier Mobility And Interface Trap Density In Ingaas Metal Oxide Semiconductor Structures Using Gated Hall Method, Thenappan Chidambaram
Extraction Of Carrier Mobility And Interface Trap Density In Ingaas Metal Oxide Semiconductor Structures Using Gated Hall Method, Thenappan Chidambaram
Legacy Theses & Dissertations (2009 - 2024)
III-V semiconductors are potential candidates to replace Si as a channel material in next generation CMOS integrated circuits owing to their superior carrier mobilities. Low density of states (DOS) and typically high interface and border trap densities (Dit) in high mobility group III-V semiconductors provide difficulties in quantification of Dit near the conduction band edge. The trap response above the threshold voltage of a MOSFET can be very fast, and conventional Dit extraction methods, based on capacitance/conductance response (CV methods) of MOS capacitors at frequencies <1MHz, cannot distinguish conducting and trapped carriers. In addition, the CV methods have to deal with high dispersion in the accumulation region that makes it a difficult task to measure the true oxide capacitance, Cox value. Another implication of these properties of III-V interfaces is an ambiguity of determination of electron density in the MOSFET channel. Traditional evaluation of carrier density by integration of the C-V curve, gives incorrect values for Dit and mobility. Here we employ gated Hall method to quantify the Dit spectrum at the high-κ oxide/III-V semiconductor interface for buried and surface channel devices using Hall measurement and capacitance-voltage data. Determination of electron density directly from Hall measurements allows for obtaining true mobility values
The Development Of Iii-V Semiconductor Mosfets For Future Cmos Applications, Andrew M. Greene
The Development Of Iii-V Semiconductor Mosfets For Future Cmos Applications, Andrew M. Greene
Legacy Theses & Dissertations (2009 - 2024)
Alternative channel materials with superior transport properties over conventional strained silicon are required for supply voltage scaling in low power complementary metal-oxide-semiconductor (CMOS) integrated circuits. Group III-V compound semiconductor systems offer a potential solution due to their high carrier mobility, low carrier effective mass and large injection velocity. The enhancement in transistor drive current at a lower overdrive voltage allows for the scaling of supply voltage while maintaining high switching performance. This thesis focuses on overcoming several material and processing challenges associated with III-V semiconductor development including a low thermal processing budget, high interface trap state density (Dit), low resistance …
An Assessment Of Critical Dimension Small Angle X-Ray Scattering Metrology For Advanced Semiconductor Manufacturing, Charles Michael Settens
An Assessment Of Critical Dimension Small Angle X-Ray Scattering Metrology For Advanced Semiconductor Manufacturing, Charles Michael Settens
Legacy Theses & Dissertations (2009 - 2024)
Simultaneous migration of planar transistors to FinFET architectures, the introduction of a plurality of materials to ensure suitable electrical characteristics, and the establishment of reliable multiple patterning lithography schemes to pattern sub-10 nm feature sizes imposes formidable challenges to current in-line dimensional metrologies. Because the shape of a FinFET channel cross-section immediately influences the electrical characteristics, the evaluation of 3D device structures requires measurement of parameters beyond traditional critical dimension (CD), including their sidewall angles, top corner rounding and footing, roughness, recesses and undercuts at single nanometer dimensions; thus, metrologies require sub-nm and approaching atomic level measurement uncertainty.
Radiation Effects In Gate-All-Around Silicon Nanowire Mosfets And Carbon Nanotube P-N Diodes, Everett Steven Comfort
Radiation Effects In Gate-All-Around Silicon Nanowire Mosfets And Carbon Nanotube P-N Diodes, Everett Steven Comfort
Legacy Theses & Dissertations (2009 - 2024)
The scaling of MOSFETs has resulted in short channel effects that increase their power consumption above acceptable levels. In order to lower the power dissipation, new device designs and materials are being considered. For example, multiple-gate MOSFETs, including the gate-all-around silicon nanowire (GAA SiNW) MOSFET, are known to reduce short channel effects. Furthermore, new high-mobility channel materials such as single-walled carbon nanotubes (SWNTs) can be integrated to allow for further scaling of the supply voltage, again aiding in lowering power dissipation.
Development Of Iii-V P-Mosfets With High-Kappa Gate Stack For Future Cmos Applications, Padmaja Nagaiah
Development Of Iii-V P-Mosfets With High-Kappa Gate Stack For Future Cmos Applications, Padmaja Nagaiah
Legacy Theses & Dissertations (2009 - 2024)
As the semiconductor industry approaches the limits of traditional silicon CMOS scaling, non-silicon materials and new device architectures are gradually being introduced to improve Si integrated circuit performance and continue transistor scaling. Recently, the replacement of SiO2 with a high-k material (HfO2) as gate dielectric has essentially removed one of the biggest advantages of Si as channel material. As a result, alternate high mobility materials are being considered to replace Si in the channel to achieve higher drive currents and switching speeds. III-V materials in particular have become of great interest as channel materials, owing to their superior electron transport …
A New Method For The Removal Of Parasitic Capacitances From Sub-100nm Mosfets Using Low-Noise Split Capacitance-Voltage Measurements, Daniel R. Steinke
A New Method For The Removal Of Parasitic Capacitances From Sub-100nm Mosfets Using Low-Noise Split Capacitance-Voltage Measurements, Daniel R. Steinke
Legacy Theses & Dissertations (2009 - 2024)
The physical shape of MOSFETs and the processing involved in their fabrication give rise to parasitic capacitances. These capacitances are typically small compared to the intrinsic channel capacitance of the device, but as MOSFETs scale into the sub-100nm gate length range, the parasitic capacitances become a significant percentage of the overall measured capacitance, resulting in a source of error in the analysis of these devices. The purpose of this work is to describe these parasitic capacitances and their origin in MOSFET structures and to propose a method for their removal for analysis. The experimental devices used for this work are …
High-K Gate Stack On Compound Semiconductor Channel Materials For Low Power, High Performance Digital Logic Applications, Rama Kambhampati
High-K Gate Stack On Compound Semiconductor Channel Materials For Low Power, High Performance Digital Logic Applications, Rama Kambhampati
Legacy Theses & Dissertations (2009 - 2024)
Group III-V compound semiconductors such as InGaAs and InGaSb are actively being considered as channel materials for low power, high performance digital logic applications due to superior carrier transport properties such as mobility and saturation velocity. The high density of interface states at high-k dielectric and III-V interface that results in pinning of Fermi level is one of the major challenges that need to be addressed before III-V CMOS becomes a mainstream technology.
Optimization And Development Of Silicon-Based Semiconductor Devices Using Tcad, Changwoo Lee
Optimization And Development Of Silicon-Based Semiconductor Devices Using Tcad, Changwoo Lee
Legacy Theses & Dissertations (2009 - 2024)
Computer simulation of the electrical and optical properties of semiconductor devices has been became as an essential tool for developing new device as well as for improving existing device. This presentation describes applications of physical device simulation: (1) design optimization of power MOSFET, which is single crystalline based silicon semiconductor device, for cryogenic temperature application and (2) two-dimensional device simulation of amorphous silicon based solar cell to develop novel photovoltaic device with high efficiency.
Investigation Of The Threshold Voltage Shift Effect Of La2o3 On Tin/Hfo2/La2o3/Sio2/Si Stacks, Ming Di
Investigation Of The Threshold Voltage Shift Effect Of La2o3 On Tin/Hfo2/La2o3/Sio2/Si Stacks, Ming Di
Legacy Theses & Dissertations (2009 - 2024)
The semiconductor industry continues to scale (shrink) transistor dimensions to both increase the number of transistors per integrated circuit and their speed. One important aspect of scaling is the need to decrease the equivalent oxide thickness of the transistor gate dielectric while minimizing leakage current. Traditional thin layer SiO2 or SiOxNy films have been replaced by higher dielectric constant film stacks Here we study one example, the HfO2/La2O3/SiO2 stack. This dissertation describes an investigation of the use of La2O3 to reduce the threshold voltage of TiN/HfO2/SiO2/Si stacks (high-k/metal gate stacks). A significant aspect of this study is the determination of …