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Full-Text Articles in Nanoscience and Nanotechnology
Exploring Gated Nanoelectronic Devices Fabricated From 1d And 2d Materials, Prathamesh A. Dhakras
Exploring Gated Nanoelectronic Devices Fabricated From 1d And 2d Materials, Prathamesh A. Dhakras
Legacy Theses & Dissertations (2009 - 2024)
One and two dimensional materials are being extensively researched toward potential application as ultra-thin body channel materials. The difficulty of implementing physical doping methods in these materials has necessitated various alternative doping schemes, the most promising of which is the electrostatic gating technique due to its reconfigurability. This dissertation explores the different fundamental devices that can be fabricated and characterized by taking advantage of the electrostatic gating of individual single-walled carbon nanotubes (SWNTs), dense SWNT networks and exfoliated 2D tungsten diselenide (WSe2) flakes.
Extraction Of Carrier Mobility And Interface Trap Density In Ingaas Metal Oxide Semiconductor Structures Using Gated Hall Method, Thenappan Chidambaram
Extraction Of Carrier Mobility And Interface Trap Density In Ingaas Metal Oxide Semiconductor Structures Using Gated Hall Method, Thenappan Chidambaram
Legacy Theses & Dissertations (2009 - 2024)
III-V semiconductors are potential candidates to replace Si as a channel material in next generation CMOS integrated circuits owing to their superior carrier mobilities. Low density of states (DOS) and typically high interface and border trap densities (Dit) in high mobility group III-V semiconductors provide difficulties in quantification of Dit near the conduction band edge. The trap response above the threshold voltage of a MOSFET can be very fast, and conventional Dit extraction methods, based on capacitance/conductance response (CV methods) of MOS capacitors at frequencies <1MHz, cannot distinguish conducting and trapped carriers. In addition, the CV methods have to deal with high dispersion in the accumulation region that makes it a difficult task to measure the true oxide capacitance, Cox value. Another implication of these properties of III-V interfaces is an ambiguity of determination of electron density in the MOSFET channel. Traditional evaluation of carrier density by integration of the C-V curve, gives incorrect values for Dit and mobility. Here we employ gated Hall method to quantify the Dit spectrum at the high-κ oxide/III-V semiconductor interface for buried and surface channel devices using Hall measurement and capacitance-voltage data. Determination of electron density directly from Hall measurements allows for obtaining true mobility values
Development Of Iii-V P-Mosfets With High-Kappa Gate Stack For Future Cmos Applications, Padmaja Nagaiah
Development Of Iii-V P-Mosfets With High-Kappa Gate Stack For Future Cmos Applications, Padmaja Nagaiah
Legacy Theses & Dissertations (2009 - 2024)
As the semiconductor industry approaches the limits of traditional silicon CMOS scaling, non-silicon materials and new device architectures are gradually being introduced to improve Si integrated circuit performance and continue transistor scaling. Recently, the replacement of SiO2 with a high-k material (HfO2) as gate dielectric has essentially removed one of the biggest advantages of Si as channel material. As a result, alternate high mobility materials are being considered to replace Si in the channel to achieve higher drive currents and switching speeds. III-V materials in particular have become of great interest as channel materials, owing to their superior electron transport …