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Selected Works

2013

Silicon

Articles 1 - 2 of 2

Full-Text Articles in Nanoscience and Nanotechnology

Spectroscopy Of A Deterministic Single-Donor Device In Silicon, M. Fuechsle, J. A. Miwa, S. Mahapatra, H. Ryu, S. Lee, O. Warschkow, L. C. L. Hollenberg, G. Klimeck, M. Y. Simmons Nov 2013

Spectroscopy Of A Deterministic Single-Donor Device In Silicon, M. Fuechsle, J. A. Miwa, S. Mahapatra, H. Ryu, S. Lee, O. Warschkow, L. C. L. Hollenberg, G. Klimeck, M. Y. Simmons

Gerhard Klimeck

We present a single electron transistor (SET) based on an individual phosphorus dopant atom in an epitaxial silicon environment. Using scanning tunneling microscope (STM) hydrogen lithography, the single impurity is deterministically placed with a spatial accuracy of ±1 lattice site within a donor-based transport device. Low temperature transport measurements confirm the presence of the single donor and show that the donor charge state can be precisely controlled via gate voltages. We observe a charging energy that is remarkably similar to the value expected for isolated P donors in bulk silicon, which is in sharp contrast to previous experiments on single-dopant …


Toward Surround Gates On Vertical Single-Walled Carbon Nanotube Devices, Aaron D. Franklin, Robert A. Sayer, Timothy D. Sands, Timothy S. Fisher, David B. Janes Oct 2013

Toward Surround Gates On Vertical Single-Walled Carbon Nanotube Devices, Aaron D. Franklin, Robert A. Sayer, Timothy D. Sands, Timothy S. Fisher, David B. Janes

Robert A Sayer

The one-dimensional, cylindrical nature of single-walled carbon nanotubes (SWCNTs) suggests that the ideal gating geometry for nanotube field-effect transistors (FETs) is a surround gate (SG). Using vertical SWCNTs templated in porous anodic alumina, SGs are formed using top-down processes for the dielectric/metal depositions and definition of the channel length. Surround gates allow aggressive scaling of the channel to 25% of the length attainable with a bottom-gate geometry without incurring short-channel effects. The process demonstrated here for forming SGs on vertical SWCNTs is amenable for large-scale fabrication of multinanotube FETs.