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Articles 1 - 7 of 7
Full-Text Articles in Nanoscience and Nanotechnology
Statistical And Variational Modeling And Analysis Of Passive Integrated Photonic Devices, Norbert Dinyi Agbodo
Statistical And Variational Modeling And Analysis Of Passive Integrated Photonic Devices, Norbert Dinyi Agbodo
Legacy Theses & Dissertations (2009 - 2024)
The success of Si as a platform for photonic devices and the associated availabilityof wafer-scale, ultra-high resolution lithography for Si CMOS has helped lead to the rapid advance of Si-based integrated photonics manufacturing over the past decade. This evolution is nearing the point of integration of Si-based photonics together with Si-CMOS for compact, high speed, high bandwidth, and cost-effective devices. However, due to the sensitive nature of passive and active photonic devices, variations inherent in wafer-based fabrication processes can lead to unacceptable levels of performance variation both within a give die and across a given wafer. Fully understanding the role …
Mechanical Analysis Of A Heterogeneously Integrated Silicon Photonic Interposer, Erica Charlene Graham
Mechanical Analysis Of A Heterogeneously Integrated Silicon Photonic Interposer, Erica Charlene Graham
Legacy Theses & Dissertations (2009 - 2024)
Overcoming the bandwidth bottleneck in conventional interconnects necessitates transitioning to alternative scaling paradigms. Silicon (Si) photonics is considered a disruptive technology, capable of meeting the growing demands for higher bandwidth, low latency, and power efficiency. By leveraging the intrinsic properties of optical signals and manufacturing compatibility of Si, the co-integration of Si photonics and complementary-metal-oxide-semiconductor (CMOS) circuitry leading to terabit data speeds for next generation data communication can be realized. Heterogeneously integrating Si photonic functionality with well-established CMOS technology in an Si photonic interposer architecture simultaneously provides independent optimization as well as close integration of both technologies in one platform. …
The Development Of Iii-V Semiconductor Mosfets For Future Cmos Applications, Andrew M. Greene
The Development Of Iii-V Semiconductor Mosfets For Future Cmos Applications, Andrew M. Greene
Legacy Theses & Dissertations (2009 - 2024)
Alternative channel materials with superior transport properties over conventional strained silicon are required for supply voltage scaling in low power complementary metal-oxide-semiconductor (CMOS) integrated circuits. Group III-V compound semiconductor systems offer a potential solution due to their high carrier mobility, low carrier effective mass and large injection velocity. The enhancement in transistor drive current at a lower overdrive voltage allows for the scaling of supply voltage while maintaining high switching performance. This thesis focuses on overcoming several material and processing challenges associated with III-V semiconductor development including a low thermal processing budget, high interface trap state density (Dit), low resistance …
Understanding Defect Interactions In Si Ultra-Shallow P-N Junctions Formed By Very Low Energy Boron Implantation, Lakshmanan H. Vanamurthy
Understanding Defect Interactions In Si Ultra-Shallow P-N Junctions Formed By Very Low Energy Boron Implantation, Lakshmanan H. Vanamurthy
Legacy Theses & Dissertations (2009 - 2024)
One of the biggest challenges in the scaling of CMOS devices is the formation of a highly activated, abrupt, defect free Source drain extension (SDE) region. This is especially difficult with p-FET's because of the (1) Boron diffusion co-efficient enhancement from Transient enhanced diffusion (TED) and (2) low solid solubility of
Graphene-Based Post-Cmos Architecture, Sansiri Tanachutiwat
Graphene-Based Post-Cmos Architecture, Sansiri Tanachutiwat
Legacy Theses & Dissertations (2009 - 2024)
The semiconductor industry relies on CMOS technology which is nearing its scaling limitations. In order to continue the historical growth rate of the device density of digital logic chips, novel nanomaterials and nanodevices will need to be developed.
Development Of Iii-V P-Mosfets With High-Kappa Gate Stack For Future Cmos Applications, Padmaja Nagaiah
Development Of Iii-V P-Mosfets With High-Kappa Gate Stack For Future Cmos Applications, Padmaja Nagaiah
Legacy Theses & Dissertations (2009 - 2024)
As the semiconductor industry approaches the limits of traditional silicon CMOS scaling, non-silicon materials and new device architectures are gradually being introduced to improve Si integrated circuit performance and continue transistor scaling. Recently, the replacement of SiO2 with a high-k material (HfO2) as gate dielectric has essentially removed one of the biggest advantages of Si as channel material. As a result, alternate high mobility materials are being considered to replace Si in the channel to achieve higher drive currents and switching speeds. III-V materials in particular have become of great interest as channel materials, owing to their superior electron transport …
Investigation Of The Threshold Voltage Shift Effect Of La2o3 On Tin/Hfo2/La2o3/Sio2/Si Stacks, Ming Di
Investigation Of The Threshold Voltage Shift Effect Of La2o3 On Tin/Hfo2/La2o3/Sio2/Si Stacks, Ming Di
Legacy Theses & Dissertations (2009 - 2024)
The semiconductor industry continues to scale (shrink) transistor dimensions to both increase the number of transistors per integrated circuit and their speed. One important aspect of scaling is the need to decrease the equivalent oxide thickness of the transistor gate dielectric while minimizing leakage current. Traditional thin layer SiO2 or SiOxNy films have been replaced by higher dielectric constant film stacks Here we study one example, the HfO2/La2O3/SiO2 stack. This dissertation describes an investigation of the use of La2O3 to reduce the threshold voltage of TiN/HfO2/SiO2/Si stacks (high-k/metal gate stacks). A significant aspect of this study is the determination of …