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Full-Text Articles in Nanoscience and Nanotechnology
Statistical And Variational Modeling And Analysis Of Passive Integrated Photonic Devices, Norbert Dinyi Agbodo
Statistical And Variational Modeling And Analysis Of Passive Integrated Photonic Devices, Norbert Dinyi Agbodo
Legacy Theses & Dissertations (2009 - 2024)
The success of Si as a platform for photonic devices and the associated availabilityof wafer-scale, ultra-high resolution lithography for Si CMOS has helped lead to the rapid advance of Si-based integrated photonics manufacturing over the past decade. This evolution is nearing the point of integration of Si-based photonics together with Si-CMOS for compact, high speed, high bandwidth, and cost-effective devices. However, due to the sensitive nature of passive and active photonic devices, variations inherent in wafer-based fabrication processes can lead to unacceptable levels of performance variation both within a give die and across a given wafer. Fully understanding the role …
Extraction Of Carrier Mobility And Interface Trap Density In Ingaas Metal Oxide Semiconductor Structures Using Gated Hall Method, Thenappan Chidambaram
Extraction Of Carrier Mobility And Interface Trap Density In Ingaas Metal Oxide Semiconductor Structures Using Gated Hall Method, Thenappan Chidambaram
Legacy Theses & Dissertations (2009 - 2024)
III-V semiconductors are potential candidates to replace Si as a channel material in next generation CMOS integrated circuits owing to their superior carrier mobilities. Low density of states (DOS) and typically high interface and border trap densities (Dit) in high mobility group III-V semiconductors provide difficulties in quantification of Dit near the conduction band edge. The trap response above the threshold voltage of a MOSFET can be very fast, and conventional Dit extraction methods, based on capacitance/conductance response (CV methods) of MOS capacitors at frequencies <1MHz, cannot distinguish conducting and trapped carriers. In addition, the CV methods have to deal with high dispersion in the accumulation region that makes it a difficult task to measure the true oxide capacitance, Cox value. Another implication of these properties of III-V interfaces is an ambiguity of determination of electron density in the MOSFET channel. Traditional evaluation of carrier density by integration of the C-V curve, gives incorrect values for Dit and mobility. Here we employ gated Hall method to quantify the Dit spectrum at the high-κ oxide/III-V semiconductor interface for buried and surface channel devices using Hall measurement and capacitance-voltage data. Determination of electron density directly from Hall measurements allows for obtaining true mobility values
Investigation Of The Threshold Voltage Shift Effect Of La2o3 On Tin/Hfo2/La2o3/Sio2/Si Stacks, Ming Di
Investigation Of The Threshold Voltage Shift Effect Of La2o3 On Tin/Hfo2/La2o3/Sio2/Si Stacks, Ming Di
Legacy Theses & Dissertations (2009 - 2024)
The semiconductor industry continues to scale (shrink) transistor dimensions to both increase the number of transistors per integrated circuit and their speed. One important aspect of scaling is the need to decrease the equivalent oxide thickness of the transistor gate dielectric while minimizing leakage current. Traditional thin layer SiO2 or SiOxNy films have been replaced by higher dielectric constant film stacks Here we study one example, the HfO2/La2O3/SiO2 stack. This dissertation describes an investigation of the use of La2O3 to reduce the threshold voltage of TiN/HfO2/SiO2/Si stacks (high-k/metal gate stacks). A significant aspect of this study is the determination of …