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Full-Text Articles in Nanoscience and Nanotechnology
Low-Temperature Fabrication Process For Integrated High-Aspect Ratio Metal Oxide Nanostructure Semiconductor Gas Sensors, William Paul Clavijo
Low-Temperature Fabrication Process For Integrated High-Aspect Ratio Metal Oxide Nanostructure Semiconductor Gas Sensors, William Paul Clavijo
Theses and Dissertations
This work presents a new low-temperature fabrication process of metal oxide nanostructures that allows high-aspect ratio zinc oxide (ZnO) and titanium dioxide (TiO2) nanowires and nanotubes to be readily integrated with microelectronic devices for sensor applications. This process relies on a new method of forming a close-packed array of self-assembled high-aspect-ratio nanopores in an anodized aluminum oxide (AAO) template in a thin (2.5 µm) aluminum film deposited on a silicon and lithium niobate substrate (LiNbO3). This technique is in sharp contrast to traditional free-standing thick film methods and the use of an integrated thin aluminum film …
Assessing The Mvs Model For Nanotransistors, Siyang Liu, Xingshu Sun, Mark S. Lundstrom
Assessing The Mvs Model For Nanotransistors, Siyang Liu, Xingshu Sun, Mark S. Lundstrom
The Summer Undergraduate Research Fellowship (SURF) Symposium
A simple semi-empirical compact MOSFET model has been developed, which is called MIT virtual source (MVS) model. Compare to other model used in industry, MVS model requires only a few parameters, most of which can be directly obtained from experiment, and produce accurate results. One aim of this paper is to test the applicability of the MVS model to transistor made from MoS2 rather than silicon. Another target is to determine the sustainability of the MVS model under different transistor tests. To achieve these goals, the MVS model will be used to fit the experimental data on MoS2 …
Development Of Iii-V P-Mosfets With High-Kappa Gate Stack For Future Cmos Applications, Padmaja Nagaiah
Development Of Iii-V P-Mosfets With High-Kappa Gate Stack For Future Cmos Applications, Padmaja Nagaiah
Legacy Theses & Dissertations (2009 - 2024)
As the semiconductor industry approaches the limits of traditional silicon CMOS scaling, non-silicon materials and new device architectures are gradually being introduced to improve Si integrated circuit performance and continue transistor scaling. Recently, the replacement of SiO2 with a high-k material (HfO2) as gate dielectric has essentially removed one of the biggest advantages of Si as channel material. As a result, alternate high mobility materials are being considered to replace Si in the channel to achieve higher drive currents and switching speeds. III-V materials in particular have become of great interest as channel materials, owing to their superior electron transport …