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Full-Text Articles in Electrical and Computer Engineering
Reconfigurable Intelligent Optical Backplane For Parallel Computing And Communications, Ted H. Szymanski, Harvard Scott Hinton
Reconfigurable Intelligent Optical Backplane For Parallel Computing And Communications, Ted H. Szymanski, Harvard Scott Hinton
H. Scott Hinton
A reconfigurable intelligent optical backplane architecture for parallel computing and communications is described. The backplane consists of a large number of reconfigurable optical channels organized in a ring with relatively simple point-to-point optical interconnections between neighboring smart-pixel arrays. The intelligent backplane can implement (l) dynamically reconfigurable connections between any printed circuit boards, (2) dynamic embeddings of classical interconnection networks such as buses, rings, multidimensional meshes, hypercubes, shuffles, and crossbars, (3) multipoint switching, (4) sorting, (5) parallel-prefix operations, (6) pattern-matching operations, (7) snoopy caches and intelligent memory systems, and (8) media-access control functions. The smart-pixel arrays can be enhanced to include …
Design, Modeling, And Characterization Of Fet-Seed Smart Pixel Transceiver Arrays For Optical Backplanes, David V. Plant, Alain Z. Shang, Marcos R. Otazo, David R. Rolston, Brian Robertson, Harvard Scott Hinton
Design, Modeling, And Characterization Of Fet-Seed Smart Pixel Transceiver Arrays For Optical Backplanes, David V. Plant, Alain Z. Shang, Marcos R. Otazo, David R. Rolston, Brian Robertson, Harvard Scott Hinton
Electrical and Computer Engineering Faculty Publications
The design, modeling, and characterization of FET-SEED smart pixel transceiver arrays fabricated for application in optical backplanes are presented. Results of digital and analog measurements on 4×4 transmitter arrays and 4×4 receiver arrays, packaged at the printed circuit-board level, will be presented. In addition, these results will be compared to device and circuit models developed for these optoelectronics. Finally, the description of the successful application of these optoelectronics to interconnect two printed circuit boards will be described.
A Hybrid-Seed Smart Pixel Array For A Four-Stage Intelligent Optical Backplane Demonstrator, David R. Rolston, David V. Plant, Ted H. Szymanski, Harvard Scott Hinton, W. S. Hsiao, Michael H. Ayliffe, David Kabal, Michael B. Venditti, P. Desai, Ashok V. Krishnamoorthy, Keith W. Goossen, J. A. Walker, B. Tseng, S. P. Hui, J. C. Cunningham, W. Y. Jan
A Hybrid-Seed Smart Pixel Array For A Four-Stage Intelligent Optical Backplane Demonstrator, David R. Rolston, David V. Plant, Ted H. Szymanski, Harvard Scott Hinton, W. S. Hsiao, Michael H. Ayliffe, David Kabal, Michael B. Venditti, P. Desai, Ashok V. Krishnamoorthy, Keith W. Goossen, J. A. Walker, B. Tseng, S. P. Hui, J. C. Cunningham, W. Y. Jan
Electrical and Computer Engineering Faculty Publications
This paper describes the VLSI design, layout, and testing of a Hybrid-SEED smart pixel array for a four-stage intelligent optical backplane. The Hybrid-SEED technology uses CMOS silicon circuitry with GaAs-AlGaAs multiple-quantum-well modulators and detectors. The chip has been designed based on the HyperPlane architecture and is composed of four smart pixels which act as a logical 4-bit parallel optical channel. It has the ability to recognize a 4-bit address header, inject electrical data onto the backplane, retransmit optical data, and extract optical data from the backplane. In addition, the smart pixel array can accommodate for optical inversions and bit permutations …
An Atm-Based Intelligent Optical Backplane Using Cmos-Seed Smart Pixel Arrays And Free- Space Optical Interconnect Modules, Dominic J. Goodwill, Kent E. Devenport, Harvard Scott Hinton
An Atm-Based Intelligent Optical Backplane Using Cmos-Seed Smart Pixel Arrays And Free- Space Optical Interconnect Modules, Dominic J. Goodwill, Kent E. Devenport, Harvard Scott Hinton
Electrical and Computer Engineering Faculty Publications
The architecture, smart pixel array chip design, and optical design of an intelligent free-space digital optical backplane for ATM switching are presented. The smart pixel chip uses reflective SEED (self-electrooptic effect device) optical modulators and detectors flip-chip bonded to CMOS circuitry. This chip is one of the most complex designs ever reported in this technology, and it operates at a simulated backplane clock rate of 125 MHz. The low-loss optical system employs f/4 diffractive minilenses and microlenses to interconnect clusters of smart pixels, and it is shown to allow 2060 connections per chip if 1-cm2 -sized smart pixel chips are …