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CMOS

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Full-Text Articles in Electrical and Computer Engineering

Cmos Receiver Design For 802.11ac Standard Using Offline Calibrated Active Inductor Based Band Pass Filter In 90 Nm Technology, Shuo Li Jan 2019

Cmos Receiver Design For 802.11ac Standard Using Offline Calibrated Active Inductor Based Band Pass Filter In 90 Nm Technology, Shuo Li

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Wireless local area network is widely used in industry and people daily life. More and more mobile devices rely on this technology to perform data communication with 2.4 GHz and 5 GHz frequency band. As the development of CMOS technology is able to keep shrinking chip size and increasing circuit integration density, traditional on-chip passive inductor inefficient area consumption issue is becoming critical to receiver front end system design. In this dissertation, an active inductor-based band pass filter is studied and implemented with 90 nm technology. This active inductor design provides very small area consumption and larger quality factor compared …


Last Two Surface Range Detector For Direct Detection Multisurface Flash Lidar In 90nm Cmos Technology, Douglas Preston Jan 2017

Last Two Surface Range Detector For Direct Detection Multisurface Flash Lidar In 90nm Cmos Technology, Douglas Preston

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This thesis explores a novel detection architecture for use in a Direct-Detect Flash LIDAR system. The proposed architecture implements detection of the last two surfaces within single pixels of a target scene. The novel, focal plane integrated detector design allows for detection of objects behind sparse and/or partially reflective covering such as forest canopy. The proposed detector would be duplicated and manufactured on-chip behind each avalanche photodiode within a focal plane array. Analog outputs are used to minimize interference from digital components on the analog input signal. The proposed architecture is a low-footprint solution which requires low computational post-processing. Additionally, …


Wideband Automatic Gain Control Design In 130 Nm Cmos Process For Wireless Receiver Applications, Joseph Benito Strzelecki Jan 2015

Wideband Automatic Gain Control Design In 130 Nm Cmos Process For Wireless Receiver Applications, Joseph Benito Strzelecki

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An analog automatic gain control circuit (AGC) and mixer were implemented in 130 nm CMOS technology. The proposed AGC was intended for implementation into a wireless receiver chain. Design specifications required a 60 dB tuning range on the output of the AGC, a settling time within several microseconds, and minimum circuit complexity to reduce area usage and power consumption.

Desired AGC functionality was achieved through the use of four nonlinear variable gain amplifiers (VGAs) and a single LC filter in the forward path of the circuit and a control loop containing an RMS power detector, a multistage comparator, and a …


Circuit Techniques On Improving Timing And Noise In Dynamic Cmos, Arvind Vaidyanadeswaran Jan 2011

Circuit Techniques On Improving Timing And Noise In Dynamic Cmos, Arvind Vaidyanadeswaran

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Dynamic CMOS are widely employed in high-performance CMOS chips due to high speed and less area in comparison with Static CMOS. However, Dynamic CMOS circuits are inherently less noise tolerant than Static CMOS circuits. This problem becomes more severe with aggressive technology scaling into nanometer process, particularly caused by the charge sharing, the sub-threshold leakage current, the power rail noise and the crosstalk noise. In this thesis, circuit techniques on improving both timing and noise of Dynamic CMOS are presented. A comparison with previous reported work is also presented. Simulations proved that the proposed circuit techniques can achieve a high …


High-Frequency Wide-Range All Digital Phase Locked Loop In 90nm Cmos, Prashanth Muppala Jan 2011

High-Frequency Wide-Range All Digital Phase Locked Loop In 90nm Cmos, Prashanth Muppala

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This thesis presents a high-frequency wide tuning range all digital phase locked loop (ADPLL) in 90 nm CMOS process with 1.2 V power supply. It operates in the frequency range of 2-7.2 GHz with wide linearity and high resolution. The ADPLL uses a wide frequency range digital controlled oscillator (DCO) and averaging technique to obtain fast lock time. The operation of the ADPLL includes both a frequency acquisition state and a phase acquisition state. A novel architecture is implemented in a coarse stage to obtain a monotonically increasing wide frequency range DCO for frequency acquisition and a fine control stage …


Design Of A Cmos Rf Front End Receiver In 0.18Μm Technology, Vishwas Kudur Sastry Jan 2008

Design Of A Cmos Rf Front End Receiver In 0.18Μm Technology, Vishwas Kudur Sastry

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An RF front end receiver system refers to the analog down conversion stages of the wireless communication system. The Digital base-band signals cannot be transmitted directly through wireless channels due to the properties of electromagnetic waves. The baseband signals need to be converted to analog through a digital-to-analog converter (DAC), up converted to higher frequency using an up conversion mixer and then transmitted through the channel. The received signals are down converted to base band frequency and then converted to digital again using the analog to digital converter (ADC). The processes which the analog signal undergoes at the RF front …