Electrical and Computer Engineering Commons^™

Critical Area Driven Dummy Fill Insertion To Improve Manufacturing Yield, Nishant Dhumane

Masters Theses 1911 - February 2014

Non-planar surface may cause incorrect transfer of patterns during lithography. In today’s IC manufacturing, chemical mechanical polishing (CMP) is used for topographical planarization. Since polish rates for metals and oxides are different, dummy metal fills in layout is used to minimize post-CMP thickness variability. Traditional metal fill solutions focus on satisfying density target determined by layout density analysis techniques. These solutions may potentially reduce yield by increasing probability of failure (POF) due to particulate defects and also impact design performance. Layout design solutions that minimize POF and also improve surface planarity via dummy fill insertions have competing requirements for line …

Scheduling Heuristics For Maximizing The Output Quality Of Iris Task Graphs In Multiprocessor Environment With Time And Energy Bounds, Rajeswaran Chockalingapuram Ravindran

Masters Theses 1911 - February 2014

Embedded real time applications are often subject to time and energy constraints. Real time applications are usually characterized by logically separable set of tasks with precedence constraints. The computational effort behind each of the task in the system is responsible for a physical functionality of the embedded system. In this work we mainly define theoretical models for relating the quality of the physical func- tionality to the computational load of the tasks and develop optimization problems to maximize the quality of the system subject to various constraints like time and energy. Specifically, the novelties in this work are three fold. …

A Theoretical Approach To Fault Analysis And Mitigation In Nanoscale Fabrics, Md Muwyid Uzzaman Khan

Masters Theses 1911 - February 2014

High defect rates are associated with novel nanodevice-based systems owing to unconventional and self-assembly based manufacturing processes. Furthermore, in emerging nanosystems, fault mechanisms and distributions may be very different from CMOS due to unique physical layer aspects, and emerging circuit and logic styles. Thus, theoretical fault models for nanosystems are necessary to extract detailed characteristics of fault generation and propagation. Using the intuition garnered from the theoretical analysis, modular and structural redundancy schemes can be specifically tailored to the intricacies of the fabric in order to achieve higher reliability of output signals.

In this thesis, we develop a detailed analytical …