Computer Engineering Commons^™

Study Of Parallel Programming Models On Computer Clusters With Accelerators, Chenggang Lai

Graduate Theses and Dissertations

In order to reach exascale computing capability, accelerators have become a crucial part in developing supercomputers. This work examines the potential of two latest acceleration technologies, Intel Many Integrated Core (MIC) Architecture and Graphics Processing Units (GPUs). This thesis applies three benchmarks under 3 different configurations, MPI+CPU, MPI+GPU, and MPI+MIC. The benchmarks include intensely communicating application, loosely communicating application, and embarrassingly parallel application. This thesis also carries out a detailed study on the scalability and performance of MIC processors under two programming models, i.e., offload model and native model, on the Beacon computer cluster.

According to different benchmarks, the results …

Technology Mapping, Design For Testability, And Circuit Optimizations For Null Convention Logic Based Architectures, Farhad Alibeygi Parsan

Graduate Theses and Dissertations

Delay-insensitive asynchronous circuits have been the target of a renewed research effort because of the advantages they offer over traditional synchronous circuits. Minimal timing analysis, inherent robustness against power-supply, temperature, and process variations, reduced energy consumption, less noise and EMI emission, and easy design reuse are some of the benefits of these circuits. NULL Convention Logic (NCL) is one of the mainstream asynchronous logic design paradigms that has been shown to be a promising method for designing delay-insensitive asynchronous circuits.

This dissertation investigates new areas in NCL design and test and is made of three sections. The first section discusses …

Optimizing Performance And Scalability On Hybrid Mpsocs, Hongyuan Ding

Graduate Theses and Dissertations

Hardware accelerators are capable of achieving significant performance improvement. But design- ing hardware accelerators lacks the flexibility and the productivity. Combining hardware accelerators with multiprocessor system-on-chip (MPSoC) is an alternative way to balance the flexibility, the productivity, and the performance. However, without appropriate programming model it is still a challenge to achieve parallelism on a hybrid (MPSoC) with with both general-purpose processors and dedicated accelerators. Besides, increasing computation demands with limited power budget require more energy-efficient design without performance degradation in embedded systems and mobile computing platforms. Reconfigurable computing with emerging storage technologies is an alternative to enable the optimization …

A Deep Search Architecture For Capturing Product Ontologies, Tejeshwar Sangameswaran

Graduate Theses and Dissertations

This thesis describes a method to populate very large product ontologies quickly. We discuss a deep search architecture to text-mine online e-commerce market places and build a taxonomy of products and their corresponding descriptions and parent categories. The goal is to automatically construct an open database of products, which are aggregated from different online retailers. The database contains extensive metadata on each object, which can be queried and analyzed. Such a public database currently does not exist; instead the information currently resides siloed within various organizations. In this thesis, we describe the tools, data structures and software architectures that allowed …

Software Porting Of A 3d Reconstruction Algorithm To Razorcam Embedded System On Chip, Kevin Curtis Gunn

Graduate Theses and Dissertations

A method is presented to calculate depth information for a UAV navigation system from Keypoints in two consecutive image frames using a monocular camera sensor as input and the OpenCV library. This method was first implemented in software and run on a general-purpose Intel CPU, then ported to the RazorCam Embedded Smart-Camera System and run on an ARM CPU onboard the Xilinx Zynq-7000. The results of performance and accuracy testing of the software implementation are then shown and analyzed, demonstrating a successful port of the software to the RazorCam embedded system on chip that could potentially be used onboard a …

Radiation-Hardened Delay-Insensitive Asynchronous Circuits For Multi-Bit Seu Mitigation And Data-Retaining Sel Protection, John Davis Brady

Graduate Theses and Dissertations

Radiation can have highly damaging effects on circuitry, especially for space applications, if designed without radiation-hardening mechanisms. Delay-insensitive asynchronous circuits inherently have promising potentials in mitigating the effects of radiation due to their delay insensitivity. This thesis proposes the use of two delay-insensitive asynchronous logic architectures to mitigate the effects of up to two single-event upsets (SEU) and a single-event latch-up (SEL). The multi-bit SEU mitigation with SEL protection architecture improves the original design by providing more integrity against data corruption and lock-ups caused by multi-bit SEUs, and it is expanded to simultaneously provide protection against SEL. The multi-bit SEU …

Designing Customizable Network-On-Chip With Support For Embedded Private Memory For Multi-Processor System-On-Chips, Azad Fakhari

Graduate Theses and Dissertations

The computer industry's transition to multiprocessor systems on chip (MPSoC) architectures is increasing the need for new scalable high-bandwidth on-chip communication

backbones. Network-on-Chip (NoC) interconnects are gaining interest for serving as the on-chip communication infrastructure. The most important issues to be considered in designing a NoC are topology, routing algorithm, flow control, and buffering and also the trade-offs between performance, power, and area.

This research proposes a custom-designed NoC specifically for MPSoCs on FPGAs. The proposed design allows the communication infrastructure to seamlessly scale as the numbers of processors within the chip increases. The design adds a new level of …

An Innovative Approach Towards Applying Chaum Mixing To Sms, Matthew Patrick Rothmeyer

Graduate Theses and Dissertations

Currently there are few user-friendly applications for anonymous communication across multiple platforms, leaving data that is often both personal and private vulnerable to malicious activity. Mobile devices such as smartphones are prime candidates for such an application as they are pervasive and have standardized communication protocols. Through the application of mixing techniques, these devices can provide anonymity for groups of individuals numbering 30 to 40 members. In this work, a Chaum mix inspired, smartphone based network that uses the Short Message Service (SMS) is described first in theory and then in implementation. This system leverages both techniques used by current …