Computer Engineering Commons^™

Transition Faults And Transition Path Delay Faults: Test Generation, Path Selection, And Built-In Generation Of Functional Broadside Tests, Bo Yao

Open Access Dissertations

As the clock frequency and complexity of digital integrated circuits increase rapidly, delay testing is indispensable to guarantee the correct timing behavior of the circuits. In this dissertation, we describe methods developed for three aspects of delay testing in scan-based circuits: test generation, path selection and built-in test generation.

We first describe a deterministic broadside test generation procedure for a path delay fault model named the transition path delay fault model, which captures both large and small delay defects. Under this fault model, a path delay fault is detected only if all the individual transition faults along the path are …