Computer Engineering Commons^™

A Nano-Drone Safety Architecture, Connor J. Sexton

Master's Theses

As small-form factor drones grow more intelligent, they increasingly require more sophisticated capabilities to record sensor data and system state, ensuring safe and improved operation. Already regulations for black boxes, electronic data recorders (EDRs), for determining liabilities and improving the safety of large-form factor autonomous vehicles are becoming established. Conventional techniques use hardened memory storage units that conserve all sensor (visual) and system operational state; and N-way redundant models for detecting uncertainty in system operation. For small-form factor drones, which are highly limited by weight, power, and computational resources, these techniques become increasingly prohibitive. In this paper, we propose a …

Splicecube Architecture: An Extensible Wi-Fi Monitoring Architecture For Smart-Home Networks, Namya Malik

Dartmouth College Master’s Theses

The vision of smart homes is rapidly becoming a reality, as the Internet of Things and other smart devices are deployed widely. Although smart devices offer convenience, they also create a significant management problem for home residents. With a large number and variety of devices in the home, residents may find it difficult to monitor, or even locate, devices. A central controller that brings all the home’s smart devices under secure management and a unified interface would help homeowners and residents track and manage their devices.

We envision a solution called the SPLICEcube whose goal is to detect smart devices, …

A Compiler Target Model For Line Associative Registers, Paul S. Eberhart

Theses and Dissertations--Electrical and Computer Engineering

LARs (Line Associative Registers) are very wide tagged registers, used for both register-wide SWAR (SIMD Within a Register )operations and scalar operations on arbitrary fields. LARs include a large data field, type tags, source addresses, and a dirty bit, which allow them to not only replace both caches and registers in the conventional memory hierarchy, but improve on both their functions. This thesis details a LAR-based architecture, and describes the design of a compiler which can generate code for a LAR-based design. In particular, type conversion, alignment, and register allocation are discussed in detail.

Ecs Game Engine Design, Daniel Masamune Hall

Computer Engineering

Game programming design and organization can be difficult and complicated. To simplify the development process, frameworks with an array of tools and utilities known as game engines are used. The main goal of this project is to explore game engine designs and develop a design for a modular and expandable game engine. The designs covered in this paper are Object Oriented Programing (OOP) and two Entity Component System (ECS). OOP designs, commonly used in computer science, use a hierarchy of objects to share functionality. ECS designs are based off of the concepts Composition over inheritance in which objects contain features …

Asynchronous Mips Processors: Educational Simulations, Robert L. Webb

Master's Theses

The system clock has been omnipresent in most mainstream chip designs. While simplifying many design problems the clock has caused the problems of clock skew, high power consumption, electromagnetic interference, and worst-case performance. In recent years, as the timing constraints of synchronous designs have been squeezed ever tighter, the efficiencies of asynchronous designs have become more attractive. By removing the clock, these issues can be mitigated. How- ever, asynchronous designs are generally more complex and difficult to debug. In this paper I discuss the advantages of asynchronous processors and the specifics of some asynchronous designs, outline the roadblocks to asynchronous …