Computer Engineering Commons^™

Design And Implementation Of An Instruction Set Architecture And An Instruction Execution Unit For The Rez9 Coprocessor System, Daniel Spencer Anderson

UNLV Theses, Dissertations, Professional Papers, and Capstones

While the use of RNS has provided groundbreaking theory and progress in this field, the applications still lack viable testing platforms to test and verify the theory. This Thesis outlines the processing of developing an instruction set architecture (ISA) and an instruction execution unit (IEU) to help make the first residue based general processor a viable testing platform to address the mentioned problems.

Consider a 32-bit ripple adder. The delay on this device will be 32N where N is the delay for each adder to complete its operation. The delay of this process is due to the need to propagate …

On High-Performance Parallel Fixed-Point Decimal Multiplier Designs, Ming Zhu

UNLV Theses, Dissertations, Professional Papers, and Capstones

High-performance, area-efficient hardware implementation of decimal multiplication is preferred to slow software simulations in a number of key scientific and financial application areas, where errors caused by converting decimal numbers into their approximate binary representations are not acceptable.

Multi-digit parallel decimal multipliers involve two major stages: (i) the partial product generation (PPG) stage, where decimal partial products are determined by selecting the right versions of the pre-computed multiples of the multiplicand, followed by (ii) the partial product accumulation (PPA) stage, where all the partial products are shifted and then added together to obtain the final multiplication product. In this thesis, …

High-Performance, Scalable Optical Network-On-Chip Architectures, Xianfang Tan

UNLV Theses, Dissertations, Professional Papers, and Capstones

The rapid advance of technology enables a large number of processing cores to be integrated into a single chip which is called a Chip Multiprocessor (CMP) or a Multiprocessor System-on-Chip (MPSoC) design. The on-chip interconnection network, which is the communication infrastructure for these processing cores, plays a central role in a many-core system. With the continuously increasing complexity of many-core systems, traditional metallic wired electronic networks-on-chip (NoC) became a bottleneck because of the unbearable latency in data transmission and extremely high energy consumption on chip. Optical networks-on-chip (ONoC) has been proposed as a promising alternative paradigm for electronic NoC with …

Cpu Scheduling For Power/Energy Management On Heterogeneous Multicore Processors, Rajesh Patel

UNLV Theses, Dissertations, Professional Papers, and Capstones

Power and energy have become increasingly important concerns in the design and implementation of today's multicore/manycore chips. Many methods have been proposed to reduce a microprocessor's power usage and associated heat dissipation, including scaling a core's operating frequency. However, these techniques do not consider the dynamic performance characteristics of an executing process at runtime, the execution characteristics of the entire task to which this process belongs, the process's priority, the process's cache miss/cache reference ratio, the number of context switches and CPU migrations generated by the process, nor the system load. Also, many of the techniques that employ dynamic frequency …

Optical Network-On-Chip Architectures And Designs, Lei Zhang

UNLV Theses, Dissertations, Professional Papers, and Capstones

As indicated in the latest version of ITRS roadmap, optical wiring is a viable interconnection technology for future SoC/SiC/SiP designs that can provide broad band data transfer rates unmatchable by the existing metal/low-k dielectric interconnects. In this dissertation study, a set of different optical interconnection architectures are presented for future on-chip optical micro-networks.

Three Optical Network-on-Chip (ONoC) architectures, i.e., Wavelength Routing Optical Network-on-Chip (WRON), Redundant Wavelength Routed Optical Network (RDWRON) and Recursive Wavelength Routed Optical Network (RCWRON) are proposed. They are fully connected networks designed based on passive switching Microring Resonator (MRR) optical switches. Given enough different routing optical wavelengths, …

Data Routing In Multicore Processors Using Dimension Increment Method, Arpita H. Kadakia

UNLV Theses, Dissertations, Professional Papers, and Capstones

A Deadlock-free routing algorithm can be generated for arbitrary interconnection network using the concept of virtual channels but the virtual channels will lead to more complex algorithms and more demands of NOC resource.

In this thesis, we study a Torus topology for NOC application, design its structure and propose a routing algorithm exploiting the characteristics of NOC. We have chosen a typical 16 (4 by 4) routers Torus and propose the corresponding route algorithm. In our algorithm, all the channels are assigned 4 different dimensions (n0,n1,n2 & n3). By following the dimension increment method, we break the dependent route circles, …

Dynamic Distributed Programming And Applications To Swap Edge Problem, Feven Z. Andemeskel

UNLV Theses, Dissertations, Professional Papers, and Capstones

Link failure is a common reason for disruption in communication networks. If communication between processes of a weighted distributed network is maintained by a spanning tree T, and if one edge e of T fails, communication can be restored by finding a new spanning tree, T’. If the network is 2-edge connected, T’ can always be constructed by replacing e by a single edge, e’, of the network. We refer to e’ as a swap edge of e.

The best swap edge problem is to find the best choice of e’, that is, that e which causes the new spanning …

Processor Allocator For Chip Multiprocessors, Dawid Maksymilian Zydek

UNLV Theses, Dissertations, Professional Papers, and Capstones

Chip MultiProcessor (CMP) architectures consisting of many cores connected through Network-on-Chip (NoC) are becoming main computing platforms for research and computer centers, and in the future for commercial solutions. In order to effectively use CMPs, operating system is an important factor and it should support a multiuser environment in which many parallel jobs are executed simultaneously. It is done by the processor management system of the operating system, which consists of two components: Job Scheduler (JS) and Processor Allocator (PA). The JS is responsible for job scheduling that deals with selection of the next job to be executed, while the …